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low power stereo codec with headphone amp datasheet sgtl5000 sgtl5000 ea2 ds-0-3 description the low power stereo codec with headphone amp from freescale is designed to provide a complete audio solution for portable products needing line-in, mic-in, line-out, headphone-out, and digital i/o. deriving it?s architecture from best in class freescale integrated products that are currently on the market, the sgtl5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest fo otprints available. target markets include portable media players, gps units and smart phones. features such as capless headphone design and an internal pll help lower overall system cost. benefits and advantages ? high performance at low power ? 100db snr (-60db input) @ < 9.3mw ? extremely low power modes ? 98db snr (-60db input) @ < 4mw (1.62v vdda, 3.0v vddio, externally driven 1.2v vddd) ? small pcb footprint ? 3mmx3mm qfn ? audio processing ? allows for no cost system customization features analog inputs ? stereo line in ? support for external analog input ? codec bypass for low power ? mic ? mic bias provided (5x5mm qfn, 3x3mm qfn ta2) ? programmable mic gain ? adc ? 85db snr (-60db input) and -73db thd+n (vdda=1.8v) analog outputs ? line out ? 100db snr (-60db input) and -85db thd+n (vddio=3.3v) ? hp output ? 100db snr (-60db input) and -80db thd+n (vdda=1.8v, 16 ohm load, dac to headphone) ? 45mw max into 16 ohm load @ 3.3v ? capless design digital i/o ? i2s port to allow routing to application processor integrated digital processing ? sigmatel surround, sigmatel bass, tone control/ parametric equalizer/graphic equalizer clocking/control ? pll allows input of 8mhz to 27mhz system clock - standard audio clocks are derived from pll power supplies ? designed to operate from 1.62 to 3.6 volts i2s interface headphone / line out w/ volume audio switch adc dac i2s_dout i2s_din i2s_sclk i2s_lrclk l i n e o u t _ r l i n e o u t _ l h p _ r hp_l i2c/spi control sys_mclk pll application processor headphone speaker amp/docking station/fmtx audio processing analog in (stereo line in, mic) linein_r linein_l mic_in mic_bias mp3/fm input mic in/speech recognition i2s interface headphone / line out w/ volume audio switch adc dac i2s_dout i2s_din i2s_sclk i2s_lrclk l i n e o u t _ r l i n e o u t _ l h p _ r hp_l i2c/spi control sys_mclk pll application processor headphone speaker amp/docking station/fmtx audio processing analog in (stereo line in, mic) linein_r linein_l mic_in mic_bias mp3/fm input mic in/speech recognition note: only i 2 c is supported in the 3 mm x 3 mm
2 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet package ? 3mm x 3mm 20 pin qfn ? 5mm x 5mm 32 pin qfn copyright ? 2008 freescale, inc. all rights reserved. freescale, inc. makes no warranty for the use of its products, assumes no responsib ility for any errors which may appear in thi s document, and makes no commitment to update the information contained herein. freescale reserves the right to change or discontinue this product at any time, without notice. there are no express or implied licenses granted hereunder to desi gn or fabricate any integrated circuits based on information in this document. sigmatel and the sigmatel logo are trademarks of freescale, inc. and may be used to identify freescale products only. windows m edia and the windows logo are trademarks or registered trademarks of microsoft corpor ation in the united states and other countries. other product a nd company names con- tained herein may be trademarks of their respective owners.
sgtl5000 ea2 ds-0-3 3 sgtl5000 datasheet 1. electrical specifications 1.1. absolute maximum ratings exceeding the absolute maximum ratings shown in table 1 could cause permanent damage to sgtl5000 and is not recommended. normal operation is not guaran- teed at the absolute maximum ratings and extended exposure could affect long term reliability. 1.2. recommended operating conditions . operational specifications table 1. absolute maximum ratings parameter min max unit storage temperature -55 125 c maximum digital voltage vddd 1.98 v maximum digital i/o voltage - vddio 3.6 v maximum analog supply voltage - vdda 3.6 v maximum voltage on any digital input gnd-0.3 vddio+0.3 v maximum voltage on any analog input gnd-0.3 vdda+0.3 v table 2. recommended operating conditions parameter symbol/pin(s) min max unit ambient operating temperature ta -40 85 c digital voltage (if supplied externally) vddd 1.1 2.0 v digital i/o voltage vddio 1.62 3.6 v analog output supply vdda 1.62 3.6 v table 3. audio performance test conditions unless otherwise noted: vddio=1.8v, vdda = 1.8v, ta=25c, slave mode, fs = 48khz, mclk = 256fs, 24 bit input. parameter min typical max unit line in input level .75 vrms line in input impedance 10k ohm line in -> adc -> i2s out snr (-60db input) 85 db
4 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet thd+n -70 db frequency response +/-.11 db channel separation 79 db line in -> headphone_lineout (codec bypass mode) snr (-60db input) 98 db thd+n (10k ohm load) -87 db thd+n (16 ohm load) -87 db frequency response +/-.05 db channel separation (1khz) 82 db i2s in -> dac -> line out output level .6 vrms snr (-60db input) 95 db thd+n -85 db frequency response +/-.12 db i2s in -> dac -> headphone out - 16 ohm load output power 17 mw snr (-60db input) 100 db thd+n -80 db frequency response +/-.12 db i2s in -> dac -> headphone out - 32 ohm load output power 10 mw snr (-60db input) 95 db thd+n -86 db frequency response +/-.11 db i2s in -> dac -> headphone out - 10k ohm load snr (-60db input) 96 db thd+n -84 db frequency response +/-.11 db psrr (200mvp-p @ 1khz on vdda) 85 db table 3. audio performance test conditions unless otherwise noted: vddio=1.8v, vdda = 1.8v, ta=25c, slave mode, fs = 48khz, mclk = 256fs, 24 bit input. parameter min typical max unit
sgtl5000 ea2 ds-0-3 5 sgtl5000 datasheet table 4. audio performance test conditions unless otherwise noted: vddio=3.3v, vdda =3 .3v, ta=25c, slave mode, fs = 48khz, mclk = 256fs, 24 bit input. adc tests were conducted with refbias = -37.5%, all other tests conducted with refbias = -50% parameter min typical max unit line in input level 1 vrms line in input impedance 10k ohm line in -> adc -> i2s out snr (-60db input) 90 db thd+n -72 db frequency response +/-.11 db channel separation 80 db line in -> headphone_lineout (codec bypass mode) snr (-60db input) 102 db thd+n (10k ohm load) -89 db thd+n (16 ohm load) -87 db frequency response +/-.05 db channel separation (1khz) 81 db i2s in -> dac -> line out output level 1 vrms snr (-60db input) 100 db thd+n -88 db frequency response +/-.12 db i2s in -> dac -> headphone out - 16 ohm load output power 58 mw snr (-60db input) 98 db thd+n -86 db frequency response +/-.12 db i2s in -> dac -> headphone out - 32 ohm load output power 30 mw snr (-60db input) 100 db thd+n -88 db frequency response +/-.11 db i2s in -> dac -> headphone out - 10k ohm load
6 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 1.3. timing specifications 1.3.1. power up timing the sgtl5000 has an internal reset that is deasserted 8 sys_ mclk cycles after all power rails have been brought up. after this time communication can start.. * 1us represents 8 sys_mclk cycl es at the minimum 8mhz sys_mclk. snr (-60db input) 97 db thd+n -85 db frequency response +/-.11 db psrr (200mvp-p @ 1khz on vdda) 89 db table 5. power up timing symbol parameter min typical max unit tpc time from all supplies powered up and sys_mclk present to initial communication 1* us table 4. audio performance test conditions unless otherwise noted: vddio=3.3v, vdda =3 .3v, ta=25c, slave mode, fs = 48khz, mclk = 256fs, 24 bit input. adc tests were conducted with refbias = -37.5%, all other tests conducted with refbias = -50% parameter min typical max unit vdda vddio vddd (if used) sys_mclk tpc ctrl_data ctrl_clk ctrl_adr0_cs initial communication figure 1. power up timing
sgtl5000 ea2 ds-0-3 7 sgtl5000 datasheet 1.3.2. i2c this section provides timing for the sg tl5000 while in i2c mode (ctrl_mode = =0). 1.3.3. spi this section provides timing for the sgtl5000 while in spi mode (ctrl_mode = =1). table 6. i2c bus timing symbol parameter m in typical max unit fi2c_clk i2c serial clock frequency 400 khz ti2csh i2c start condition hold time 150 ns ti2cstsu i2c stop condition setup time 150 ns ti2cdsu i2c data input setup time to rising edge of ctrl_clk 125 ns ti2cdh i2c data input hold time from falling edge of ctrl_clk (sgtl5000 receiving data) 5ns ti2cdh i2c data input hold time from falling edge of ctrl_clk (sgtl5000 driving data) 360 ns ti2cclkl i2c ctrl_clk low time 300 ns ti2cclkh i2c ctrl_clk high time 100 ns table 7. spi bus timing symbol parameter min typical max unit fspi_clk spi serial clock frequency ??? mhz tspidsu spi data input setup time 10 ns 1/fi2c_clk ti2csh ti2cclkh ti2cclkl ti2cdsu ti2cdh ctrl_clk ctrl_data ti2cstsu figure 2. i2c timing (ctrl_mode == 0)
8 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 1.3.4. i2s the following are the specifications and timi ng for i2s port. the timing applies to all formats. tspidh spi data input hold time 10 ns tspiclkl spi ctrl_clk low time ??? ns tspiclkh spi ctrl_clk high time ??? ns tccs spi clock to chip select 60 ns tcsc spi chip select to clock 20 ns tcsl spi chip select low 20 ns tcsh spi chip select high 20 ns table 1-1. symbol parameter min typical max unit flrclk frequency of i2s_lrclk ??? 96 khz fsclk frequency of i2s_sclk 32*flrclk, 64*flrclk khz ti2s_d i2s delay 10 ns ti2s_s i2s setup time 10 ns table 7. spi bus timing symbol parameter min typical max unit 1/fspi_clk tspidh tspiclkh tspiclkl tspidsu ctrl_clk ctrl_data ctrl_ad0_cs tcsl tcsh tcsc tccs figure 3. spi timing
sgtl5000 ea2 ds-0-3 9 sgtl5000 datasheet . ti2s_h i2s hold time 10 ns table 1-1. symbol parameter min typical max unit 1/fsclk ti2s_s ti2s_d i2s_sclk i2s_lrclk in slave mode i2s_lrclk in master mode ti2s_h ti2s_d i2s_sclk i2s_din i2s_dout ti2s_s i2s_lrclk 1/flrclk figure 4. i2s interface timing
10 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 2. power consumption vddd derived internally @ 1.2v, slave mo de except for pll case, 32 ohm load on hp, conditions: -100dbfs signal input, sl ave mode unless otherwise noted, paths tested as indicated, unused paths turned off. a further 0.5- 1.0mw reduction in power is expected with ta2 silicon. table 8: power consumption: vdda=1.8v, vddio=1.8v mode current consumption (ma) power(mw) vddd vdda vddio playback (i2s->dac->headphone) 2.54 .9 6.19 playback with dap ((i2s->dap->dac- >headphone) 3.59 .9 8.08 playback/record (i2s->dac->head- phone, adc->i2s) 3.71 1.10 8.67 record (adc->i2s ) 2.29 1.06 6.02 analog playback, codec bypassed (linein->hp) 1.48 .89 4.27 standby, all analog power off .019 .002 .038 playback with pll (i2s ->dac->hp) 3.01 2.17 9.31 table 9: power consumption: vdda=3.3v, vddio=3.3v mode current consumption (ma) power(mw) vddd vdda vddio playback (i2s->dac->headphone) 3.45 .067 11.60 playback with dap ((i2s->dap->dac- >headphone) 4.49 .067 15.03 playback/record (i2s->dac->head- phone, adc->i2s) 4.67 .343 16.53 record (adc->i2s) 2.90 .296 10.56 analog playback, codec bypassed (linein->hp) 1.91 .039 6.43 standby, all analog power off .04 .002 .139
sgtl5000 ea2 ds-0-3 11 sgtl5000 datasheet playback with pll (i2s-> dac->hp) 3.92 2.76 22.05 table 9: power consumption: vdda=3.3v, vddio=3.3v mode current consumption (ma) power(mw) vddd vdda vddio
12 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 3. pinout & package info 3.1. pinout figure 5. sgtl5000 20qfn pinout 20qfn pinout u? sgtl5000_20qfn u? sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 mic_bias 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 u1 sgtl5000_ 32qfn u1 sgtl5000_ 32qfn i 2 s_sclk 2 4 n c 22 li n ei n _l 14 c pf ilt 18 vddio 2 0 n c 19 sys_mclk 2 1 i 2 s_dout 2 5 i 2 s_di n 2 6 h p _l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 g n d 1 n c 8 h p _r 2 g n d 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 n c 17 li n ei n _r 1 3 ag n d 7 i 2 s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 h p _vg n d 4 n c 9 vag 10 mic_bias 16 g n d p ad figure 6. sgtl5000 32qfn pinout
sgtl5000 ea2 ds-0-3 13 sgtl5000 datasheet 3.2. pin description table 10. 20 pin qfn pinout pin count pin name description notes 1 hp_r right headphone output analog 2 hp_vgnd headphone virtual ground analog 3 vdda analog voltage power 4 hp_l left headphone output analog 5 vag dac vag filter analog 6 lineout_r right line out analog 7 lineout_l left line out analog 8 linein_r right line in analog 9 linein_l left line in analog 10 mic microphone input analog 11 cpfilt charge pump filter analog 12 vddio digital i/o voltage power 13 sys_mclk system master clock digital 14 i2s_lrclk i2s frame clock digital 15 i2s_sclk i2s bit clock digital 16 i2s_dout i2s data output digital 17 i2s_din i2s data input digital 18 ctrl_data i2c mode: serial data (sda); spi mode: serial data input (mosi) digital 19 ctrl_clk i2c mode: serial clock (scl); spi mode: serial clock (sck) digital 20 vddd digital voltage power pad gnd ground. center pad of package is ground connection for part and must be connected to board ground. ground
14 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet table 11. 32 pin qfn pinout pin count pin name description notes 1 gnd ground ground 2 hp_r right headphone output analog 3 gnd ground ground 4 hp_vgnd headphone virtual ground analog 5 vdda analog voltage power 6 hp_l left headphone output analog 7 agnd analog ground ground 8 nc no connect digital 9 nc no connect digital 10 vag dac vag filter analog 11 lineout_r right line output analog 12 lineout_l left line output analog 13 linein_r right line input analog 14 linein_l left line input analog 15 mic microphone input analog 16 mic_bias mic bias analog 17 nc no connect 18 cpfilt charge pump filter analog 19 nc no connect 20 vddio digital i/o voltage power 21 sys_mclk system master clock digital 22 nc no connect 23 i2s_lrclk i2s frame clock digital 24 i2s_sclk i2s bit clock digital 25 i2s_dout i2s data output digital 26 i2s_din i2s data input digital
sgtl5000 ea2 ds-0-3 15 sgtl5000 datasheet 3.3. package 27 ctrl_data i2c mode: serial data (sda); spi mode: serial data input (mosi) digital 28 nc no connect 29 ctrl_clk i2c mode: serial clock (scl); spi mode: serial clock (sck) digital 30 vddd digital voltage power 31 ctrl_adr0_cs i2c mode: i2c address select 0; spi mode: spi chip select digital 32 ctrl_mode mode select for i2c or spi; when pulled low the control mode is i2c, when pulled high the control mode is spi digital pad gnd this pad should be soldered to ground. this is a suggestion for mechanical stabi lity but is not required electrically. ground table 11. 32 pin qfn pinout pin count pin name description notes
16 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet figure 7. sgtl5000 3mmx3mm 20qfn package
sgtl5000 ea2 ds-0-3 17 sgtl5000 datasheet figure 8. sgtl5000 5mmx5mm 32qfn package (sheet 1)
18 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet figure 9. sgtl5000 5mmx5mm 32qfn package (sheet 2)
sgtl5000 ea2 ds-0-3 19 sgtl5000 datasheet 4. typical connection diagrams typical connection diagrams are shown in th is section that demonstrate the flexibil- ity of the sgtl5000. both low cost and low power configurations are presented although it should be noted that all conf igurations offer a low cost design with high performance and low power. some design considerations for sgtl5000 are as follows: ? star the ground pins of the chip, vag ground, and all analog inputs/outputs to a single point, then to the ground plane ? use the widest, shortest trace possible for the hp_vgnd
20 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 5 5 4 4 3 3 2 2 1 1 vdda (1.62v to 3.6v) vddio (1.62v to 3.6v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk notes: 1. the above circuit shows vddd (pin 20) being derived internally. for lowest power operation vddd can be driven from an external 1.2v supply with .1uf of decoupling to ground. 2. the above circuit shows a mic bias circuit derived from an external supply (vddio). 20qfn typical connection diagram c? 1uf c? 1uf c? 0.1uf c? 0.1uf r? 2.2k r? 2.2k c? .1uf c? .1uf c? 0.1uf c? 0.1uf j? audio jack j? audio jack 2 5 1 4 3 c? 1uf c? 1uf c? 1uf c? 1uf r? 2.2k r? 2.2k x? mic x? mic 1 2 c? 1uf c? 1uf c? .1uf c? .1uf u? sgtl5000_20qfn u? sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 c? .1uf c? .1uf + c? 10uf 6.3v + c? 10uf 6.3v
sgtl5000 ea2 ds-0-3 21 sgtl5000 datasheet vddio (=3.1v) vdda (=1.6v) vddd (=1.2v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk 20qfn typical connection diagram - lowest power configuration 1. vddd is driven externally by 1.2v supply. 2. vdda is driven at 1.6v 3. vddio is driven at 3.1v c8 0.1uf c8 0.1uf c9 1uf c9 1uf c1 0.1uf c1 0.1uf u1 sgtl5000_20qfn u1 sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 + c11 10uf 6.3v + c11 10uf 6.3v j1 audio jack j1 audio jack 2 5 1 4 3 c2 220uf c2 220uf c12 1uf c12 1uf r1 2.2k r1 2.2k x1 mic x1 mic 1 2 c3 220uf c3 220uf c13 1uf c13 1uf c7 .1uf c7 .1uf c4 .1uf c4 .1uf c10 1uf c10 1uf c5 0.1uf c5 0.1uf r2 2.2k r2 2.2k c6 .1uf c6 .1uf
22 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet vdd (= 3 .1v to 3 .6v) vdd (= 3 .1v to 3 .6v) ctrl_clk 6,7 i 2 s_sclk 7 ctrl_data 6,7 i 2 s_di n 7 i 2 s_dout 7 sys_mclk i 2 s_lrclk 7 li n e_i n _l 4 li n e_i n _r 4 li n e_out_r 5 li n e_out_l 5 notes: 1. vddd is derived internally (no need for external cap) 2. vdda and vddio are supplied from same voltage that is between 3.1v and 3.6v. by using the same voltage this allows removal of power decoupling cap. by using a voltage above 3.1v the cap connected to cpfilt can be removed. 32qfn t ypical c onnection d iagram - l owest c ost c onfiguration solder pad to gnd c 2 .1 uf c 2 .1 uf c8 1 uf c8 1 uf j1 a u d io j ac k j1 a u d io j ac k 2 5 1 4 3 u1 sgtl5000_ 32qfn u1 sgtl5000_ 32qfn i 2 s_sclk 2 4 n c 22 li n ei n _l 14 c pf ilt 18 vddio 2 0 n c 19 sys_mclk 2 1 i 2 s_dout 2 5 i 2 s_di n 2 6 h p _l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 g n d 1 n c 8 h p _r 2 g n d 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 n c 17 li n ei n _r 1 3 ag n d 7 i 2 s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 h p _vg n d 4 n c 9 vag 10 mic_bias 16 g n d p ad c7 1 uf c7 1 uf c 3 0.1 uf c 3 0.1 uf c6 1 uf c6 1 uf c4 1 uf c4 1 uf c5 1 uf c5 1 uf c1 0.1 uf c1 0.1 uf x1 mic x1 mic 1 2
sgtl5000 ea2 ds-0-3 23 sgtl5000 datasheet vddio (= 3 .1v) vdda (=1.6v) vddd (=1. 2 v) ctrl_clk 6,7 i 2 s_sclk 7 ctrl_data 6,7 i 2 s_di n 7 i 2 s_dout 7 sys_mclk i 2 s_lrclk 7 li n e_i n _l 4 li n e_i n _r 4 li n e_out_r 5 li n e_out_l 5 32qfn t ypical c onnection d iagram - l owest power c onfiguration solder pad to gnd 1. vddd is driven externally by 1.2v supply. 2. vdda is driven at 1.6v 3. vddio is driven at 3.1v c 322 0 uf c 322 0 uf c 222 0 uf c 222 0 uf c5 0.1 uf c5 0.1 uf j1 a u d io j ac k j1 a u d io j ac k 2 5 1 4 3 c6 .1 uf c6 .1 uf c4 0.1 uf c4 0.1 uf c7 0.1 uf c7 0.1 uf x1 mic x1 mic 1 2 c8 1 uf c8 1 uf c1 0.1 uf c1 0.1 uf c9 1 uf c9 1 uf c11 1 uf c11 1 uf c10 1 uf c10 1 uf c1 2 1 uf c1 2 1 uf u1 sgtl5000_ 32qfn u1 sgtl5000_ 32qfn i 2 s_sclk 2 4 n c 22 li n ei n _l 14 c pf ilt 18 vddio 2 0 n c 19 sys_mclk 2 1 i 2 s_dout 2 5 i 2 s_di n 2 6 h p _l 6 ctrl_data 2 7 n c 2 8 ctrl_clk 2 9 g n d 1 n c 8 h p _r 2 g n d 3 vdda 5 li n eout_l 1 2 li n eout_r 11 mic 15 n c 17 li n ei n _r 1 3 ag n d 7 i 2 s_lrclk 23 vddd 3 0 ctrl_adr0_cs 3 1 ctrl_mode 32 h p _vg n d 4 n c 9 vag 10 mic_bias 16 g n d p ad
24 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet vddio (=3.1v) vdda (=1.6v) vddd (=1.2v) line_in_left line_in_right line_out_left line_out_right i2c_clk i2c_data i2s_sclk i2sdout i2s_din i2s_lrclk sys_mclk 20qfn typical connection diagram - lowest power configuration 1. vddd is driven externally by 1.2v supply. 2. vdda is driven at 1.6v 3. vddio is driven at 3.1v c8 0.1uf c8 0.1uf c9 1uf c9 1uf c1 0.1uf c1 0.1uf u1 sgtl5000_20qfn u1 sgtl5000_20qfn gnd pad vag 5 hp_r 1 hp_vgnd 2 vdda 3 hp_l 4 mic 10 cpfilt 11 lineout_r 6 lineout_l 7 linein_r 8 i2s_lrclk 14 i2s_din 17 i2s_dout 16 i2s_sclk 15 ctrl_clk 19 ctrl_data 18 sys_mclk 13 vddio 12 vddd 20 linein_l 9 + c11 10uf 6.3v + c11 10uf 6.3v j1 audio jack j1 audio jack 2 5 1 4 3 c2 220uf c2 220uf c12 1uf c12 1uf r1 2.2k r1 2.2k x1 mic x1 mic 1 2 c3 220uf c3 220uf c13 1uf c13 1uf c7 .1uf c7 .1uf c4 .1uf c4 .1uf c10 1uf c10 1uf c5 0.1uf c5 0.1uf r2 2.2k r2 2.2k c6 .1uf c6 .1uf
sgtl5000 ea2 ds-0-3 25 sgtl5000 datasheet 5 5 4 4 3 3 2 2 1 1 d d c c b b a a vddio vdda vddd ctrl_clk 6,7 i2s_sclk 7 ctrl_data 6,7 i2s_din 7 i2s_dout 7 sys_mclk i2s_lrclk 7 line_in_l 4 line_in_r 4 line_out_r 5 line_out_l 5 notes: 1. the above circuit shows vddd (pin 30) being derived internally. for lowest power operation vddd can be driven from an external 1.2v supply with .1uf of decoupling to ground. 2. if both vddio and vdda are below 3v, the cpfilt pin (pin 17) must be connected to a .1uf cap to ground. if either is above 3v, this cap is not needed. 3. the above shows i2c implementation as ctrl_mode (pin 32) is tied to ground). in addition, address 0 of the i2c address is 0 as ctrl_adr0_cs (pin 31) is tied to ground. 4. agnd (pin 7) should be "star" connected to the jack grounds for line in and line out and the ground side of the capacitor tied to vag. this node should via to the ground plane (or connected to ground) at a single point. 32qfn typical connection diagram solder pad to gnd j? audio jack j? audio jack 2 5 1 4 3 c? 0.1uf c? 0.1uf u? sgtl5000_32qfn u? sgtl5000_32qfn i2s_sclk 24 nc 22 linein_l 14 cpfilt 18 vddio 20 nc 19 sys_mclk 21 i2s_dout 25 i2s_din 26 hp_l 6 ctrl_data 27 nc 28 ctrl_clk 29 gnd 1 nc 8 hp_r 2 gnd 3 vdda 5 lineout_l 12 lineout_r 11 mic 15 nc 17 linein_r 13 agnd 7 i2s_lrclk 23 vddd 30 ctrl_adr0_cs 31 ctrl_mode 32 hp_vgnd 4 nc 9 vag 10 mic_bias 16 gnd pad c? 1uf c? 1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 0.1uf c? 1uf c? 1uf c? 1uf c? 1uf x? mic x? mic 1 2 c? 1uf c? 1uf r? 2.2k r? 2.2k c? 1uf c? 1uf c? 0.1uf c? 0.1uf
26 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 5. device description the sgtl5000 is a low power stereo codec with integrated headphone amplifier. it is designed to provide a complete audio solution for portable products needing line- in, mic-in, line-out, headphone-out, and digi tal i/o. deriving it?s architecture from best in class freescale integrated products that are currently on the market, the sgtl5000 is able to achieve ultra low power with very high performance and func- tionality, all in one of the smallest footprints available. target markets include por- table media players, gps units and smart phones. features such as capless headphone design and usb clocking mode (12mhz sys_mclk input) help lower overall system cost. in summary, sgtl5000 acce pts the following inputs: ? line input ? microphone input, with mic bias (mic bias only available in 32qfn version) ? digital i2s input in addition, sgtl5000 supports the following outputs: ? line output ? headphone output ? digital i2s output the following digital audio processing is incl uded to allow for product differentiation: ? digital mixer ? sigmatel surround ? sigmatel bass enhancement ? tone control, parametric equalizer, and graphic equalizer the sgtl5000 can accept an external stan dard master clock at a multiple of the sampling frequency (i.e. 256*fs, 385*fs, 512*fs). in addition it can take non stan- dard frequencies and use the internal pll to derive the audio clocks. the device supports 8khz, 11.025khz, 16khz, 22.5khz, 24khz, 32khz, 44.1khz, 48khz, 96khz sampling frequencies.
sgtl5000 ea2 ds-0-3 27 sgtl5000 datasheet 5.1. system block diagram w/ signal flow and gain map figure 10 below shows a block diagram that highlights the signal flow and gain map for the sgtl5000. to guarantee against clipping it is important that the gain in a signal path in addition to the signal level does not exceed 0db at any point. 5.2. power the sgtl5000 has a flexible power archit ecture to allow the system designer to minimize power consumption and maximi ze performance at the lowest cost. 5.2.1. external power supplies the sgtl5000 requires 2 external power supplies: vdda and vddio. an optional third external power supply vddd may be provided externally to achieve lower power. a description for the different power supplies is as follows: ? vdda: this external power supply is used for the internal analog circuitry including adc, dac, line inputs, mi c inputs, headphone outputs and refer- ence voltages. vdda supply ranges ar e shown in section 1.2. a decoupling cap should be used on vdda as shown in the typical connection diagram in section 4. ? vddio: this external power supply contro ls the digital i/o levels as well as the output level of line outputs. vddio su pply ranges are shown in section 1.2. a decoupling cap should be used on vddi o as shown in the typical connection diagram in section 4. mic gain (0db, 20db, 30db, 40db ) mic_in audio switch i2s_din adc i2s_dout mix +6db tone control /geq/peq +12db bass enhancement +6db surround avc +12db dac dac volume control -90db to 0db headphone volume control -52db to +12db ( chip_ana_hp_ctrl ) hp_out analog gain digital gain analog gain (0 to 22.5db) only gain is shown for the digital audio processing blocks. for complete description please see digital audio processing section. line out volume control ( chip_line_out_vol ) lineout line_in figure 10. system block di agram, signal flow and gain
28 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet note that if vdda and vddio are derived fr om the same voltage, a single decou- pling capacitor can be used to minimize co st. this capacitor should be placed clos- est to vdda. ? vddd: this is a digital power supply that is used for internal digital circuitry. for a low cost design, this supply can be derived from an internal regulator and no external components are required. if no external supply is applied to vddd, the internal regulator will automati cally be used. for lowest power, this supply can be driven at the lowest specified voltage gi ven in section 1.2. if an external sup- ply is used for vddd, a decoupling capacitor is recommended. vddd supply ranges are shown in section 1.2 for when externally driven. if the system drives vddd externally, an efficient switching supply should be used or or no system power savings will be realized. 5.2.2. internal power supplies the sgtl5000 has two exposed internal power supplies, vag and chargepump. ? vag is the internal voltage reference for the adc and dac. after startup the voltage of vag should be set to vdda/2 by writing chip_ref_ctrl- >vag_val . refer to programming section 6.2.1.1. the vag pin should have an external filter capacitor as shown in the typical connection diagram. ? chargepump: this power supply is used for internal analog switches. if vdda or vddio is greater than 2.7v, this supply is automatically driven from the high- est of vddio and vdda. if both vddio and vdda are less than 3.1v, then the user should turn on the charge pump function to create the chargepump rail from vddio by writing chip_ana_power->vddc _chrgpmp_powerup register. refer to programming section 6.2.1.1. ? line_out_vag is the line output voltag e reference. it should be set to vddio/2 by writing chip_line_out_ctrl->lo_vagcntrl . 5.2.3. power schemes the sgtl supports a flexible architecture and allows the system designer to mini- mize power or maximize bom savings. ? for maximum cost savings, all supplies can be run at the same voltage. ? alternatively for minimum power, the anal og and digital supplies can be run at minimum voltage while driving the digital i/o voltage at the voltage needed by the system. ? to save power, independent supplies are provided for line outputs and head- phone outputs. this allows for 1vrms line outputs while using minimal head- phone power. ? for best power, vdda should be run at the lowest possible voltage required for the maximum headphone output level. for highest performance, vdda should be run at 3.3v. for most applications a lower voltage can be used for the best performance/power combination. 5.3. reset the sgtl5000 has an intern al reset that is deasserted 8 sys_mclks after all power rails have been brought up. after this time communication can start. see sec- tion 1.3 for timing specification.
sgtl5000 ea2 ds-0-3 29 sgtl5000 datasheet 5.4. clocking clocking for the sgtl5000 is provided by a system master clock input (sys_mclk). sys_mclk should be synchronous to th e sampling rate (fs) of the i2s port. alternatively any clock betw een 8mhz and 27mhz can be provided on sys_mclk and the sgtl5000 can use an inte rnal pll to derive all internal and i2s clocks. this allows the system to us e an available clock such as 12mhz (com- mon usb clock) for sys_mclk to reduce overall system costs. 5.4.1. synchronous sys_mclk input the sgtl5000 supports vari ous combinations of sys_ mclk frequency and sam- pling frequency as shown in table 12. using a synchronous sys_mclk allows for lower power as the internal pll is not used. note 1. for a sampling frequency of 96k hz, only 256fs sys_m clk is supported 5.4.2. using the pll - asynchronous sys_mclk input an integrated pll is provided in the sgtl5000 that allows any clock from 8mhz to 27mhz to be connected to sys_mclk. this can help save system costs as a clock available elsewhere in the system can be used to derive all audio clocks using the internal pll. in this case the clock in put to sys_mclk can be asynchronous with the sampling frequency needed in the system. for example a 12mhz clock from the system processor could be used as the clock input to the sgtl5000. three register fields need to be configur ed to properly use the pll. they are chip_pll_ctrl->int_divisor , chip_pll_ctrl-> frac_divisor and chip_clk_top_ctrl->input_freq_div2 . figure 11 shows a flowchart that shows how to determine the values to program in the register fields. table 12. synchronous mclk rates clock supported rates units system master clock (sys_mclk) 256, 384, 512 fs sampling frequency (fs) 8, 11.025, 16, 22.5, 32, 44.1, 48, 96(note 1) khz
30 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet for example, when a 12mhz digital signal is placed on mclk, for a 48khz frame clock chip_clk_top_ctrl->input_freq_div2 = 0 // sys_mclk<17mhz chip_pll_ctrl->int_divisor = floor(196.608mhz/12mhz) = 16 (decimal) chip_pll_ctrl->frac_divisor = ((196.608mhz/12mhz) - 16) * 2048 = 786 (decimal) refer to pll programming note 6.2.2. 5.5. audio switch (source select switch) the audio switch is the central routing blo ck that controls the signal flow from input to output. any single input can be routed to any single or multiple outputs. any signal can be routed to the digital au dio processor (dap). the output of the dap (an input to the audio switch) can in turn be routed to any physical output. the output of the dap can not be routed into itse lf. refer to section 5.9, digital audio processing, for dap information and configuration. it should be noted that the analog bypass from line input to headphone output does not go through the audio switch. sys_mclk>17mhz? chip_clk_top_ctrl->input_freq_div2 = 1 pll_input_freq = sys_mclk/2 sampling frequency = 44.1khz? pll_output_freq=180 .6336 mhz pll_output_freq=196 .608 mhz chip_clk_top_ctrl->input_freq_div2 = 0 pll_input_freq = sys_mclk chip_pll_ctrl->int_divisor = floor (pll_output_freq/input_freq chip_pll_ctrl->frac_divisor = ((pll_output_freq/input_freq) - int_divisor) * 2048 no yes no yes figure 11. pll programming flowchart
sgtl5000 ea2 ds-0-3 31 sgtl5000 datasheet to configure a route, the chip_sss_ctrl register is used. each output from the source select switch has its own register fi eld that is used to select what input is routed to that output. for example, to route the i2s digital input through the dap and then out to the dac (headphone) outputs write sss_ctrl->dap_select to 0x1 (selects i2s_in) and sss_ctrl->dac_select to 0x3 (selects dap output). 5.6. analog input block the analog input block contains a stereo line input and a microphone input with mic bias (in the 32qfn package). either input can be routed to the adc. the line input can also configured to bypass the codec and be routed the analog input directly to the headphone output. 5.6.1. line inputs one stereo line input is provided for connection to line sources such as an fm radio or mp3 input. the source should be connected to the left and right line inputs through series cou- pling capacitors. the suggested value is shown in the typical connection diagram in section 4. as detailed in section 5.6.3, the lin e input can be routed to the adc. the line input can also be routed to the headphone output by writing chip_ana_ctrl->select_hp . this selection bypasses the adc and audio switch and routes the line input directly to the headphone output to enable a very low power pass through. 5.6.2. microphone input one mono microphone input is provided for uses such as voice recording. mic bias is provided in the 32qfn package. the mic bias is can be programmed with the chip_mic_ctrl->bias_volt registor field. values from 1.25v to 3.00v are supported in 0.25v steps. mic bias sh ould be set less than 200mv from vdda, e.g. with vdda at 1.70v, mic bias should be set no greater than 1.50v. the microphone should be connected through a series coupling capacitor. the sug- gested value is shown in the typical connection diagram. the microphone has programmable gain through the chip_mic_ctrl->gain reg- ister field. values of 0db, +2 0db, +30db and +40db are available. 5.6.3. adc the sgtl5000 contains an adc who takes its input from either the line input or a microphone. the register field chip_ana_ctrl->select_adc controls this selection. the output of the adc feeds the audio switch. the adc has its own analog gain stage that provides 0 to +22.5db of gain in 1.5db steps. a bit is available that shifts this range down by 6db to effectively provide -6db to +16.5db of gain. the adc gain is controlled in the chip_ana_adc_ctrl register.
32 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet the adc has an available zero-cross detect (zcd) that will prevent any volume change until a zero-volt crossing of the audio signal is detected. this helps in elimi- nating pop or other audio anomalies. if the adc is to be used, the chip reference bias current should not be set to -50% when in 3v mode. 5.7. analog outputs the sgtl5000 contains a single stereo dac that can be used to drive a heapdhone output and a line output. the dac receiv es its input from the audio switch. the headphone output and the line output can be driven at the same time from the dac. the headphone output can also be driven directly by the line input bypassing the adc and dac for a very low power mode of operation. the headphone output is powered by vdda while the line output is powered by vddio. this allows the headphone output to be run at the lowest possible voltage while the line output can still meet line output leve l requirements. 5.7.1. dac the dac output is routed to the headphone and the dedicated line output. the dac output has a digital volume contro l from -90db to 0db in ~.5db step sizes. this volume is shared among headphone output and line output. the register chip_dac_vol controls the dac volume. 5.7.2. headphone stereo headphone outputs are provided which can be used to drive a headphone load or a line level output. the headphone output has its own independent analog volume control with a volume range of -52db to +12db in .5db step sizes. this vol- ume control can be used in addition to the dac volume control. for best perfor- mance the dac volume control should be left at 0db until the headphone is brought to its lowest setting of -52db. the register chip_ana_hp_ctrl is used to control the headphone volume. the headphone output has an independent mu te that is controlled by the register field chip_ana_ctrl ->mute_hp . the line input is routed to th e headphone output by writing chip_ana_ctrl- >select_hp . this selection bypasses the adc and audio switch and routes the line input directly to the headphone output to enable a very low power pass through. when the line input is routed to the h eadphone output, only the headphone analog volume and mute will affect the headphone output. the headphone has an available zero cr oss detect (zcd) which, as previously described, will prevent any vo lume change until a zero-vol t crossing of the audio signal is detected. this helps in eliminating pop or other audio anomalies. 5.7.3. line outputs the sgtl5000 contains a stereo line output. the line output has a dedicated gain stage that can be used to adjust the output level. the chip_line_out_vol con- trols the line level output gain. the line outputs also have a dedicated mute that is controlled by the register field chip_ana_ctrl->mute_lo.
sgtl5000 ea2 ds-0-3 33 sgtl5000 datasheet the lineout volume is intended as maximum output level adjustm ent. it is intended to be used to set the maximum output swing. it does not have the range of a typical volume control and does not have a zero cross detect (zcd). however the dac digi- tal volume could be used if volume control is desired 5.8. digital input & output one i2s (digital audio) port is provided which supports the fo llowing formats: i2s, left justified, right justified and pcm mode. 5.8.1. i2s, left justified and right justified modes i2s, left justified and right justified modes are stereo interface formats. the i2s_sclk frequency, i2s_sclk polarity, i2s_din/dout data length, and i2s_lrclk polarity can all be change through the chip_i2s_ctrl register. for i2s, left justified and right justified formats the left subframe should always be presented first regardless of the chip_i2s_ctrl->lrpol setting. the i2s_lrclk and i2s_sclk can be programmed as master (driven to an exter- nal target) or slave (driven from an extern al source). when the clocks are in slave mode, they must be synch ronous to sys_mclk. for this reason the sgtl5000 can only operate in synchronous mode (see section 5.4) while in i2s slave mode. in master mode, the clocks will be sync hronous to sys_mclk or the output of the pll when the part is running in asynchronous mode. figure 12 shows functional examples of different common digital interface formats and their associated register settings.
34 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 5.8.2. pcm mode the i2s port can also be configured into a pcm mode (also known as dsp mode). this mode is provided to allo w connectivity to to extern al devices such as bluetooth modules. pcm mode differs from other in terface formats presented in section 5.8.1 in that the frame clock (i2s_lrclk) does not represent a different channel when high or low, but is a bit-wide pulse that marks the start of a frame. data is aligned such that the left channel data is immedi ately followed by right channel data. zero padding is filled in for the remaining bits. the data and frame clock may be config- ured to clock in on the rising or falling edge of bit clock. l n l (n-1) l01 l00 r n r (n-1) r01 r00 i2s_lrclk i2s_sclk i2s_din, dout i2s format (n = bit length) chip_i2s0_ctrl field values: (sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 0; lralign = 0; lrpol = 0) l n l n l (n-1) l 1 l 0 r n r (n-1) r 1 r 0 i2s_lrclk i2s_sclk i2s_din, dout left justified format (n = bit length) chip_i2s0_ctrl field values: (sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 0; lralign = 1; lrpol = 0) l n l (n-1) l n l (n-1) l 0 r n r (n-1) r0 i2s_lrclk i2s_sclk i2s_din, dout right justified format (n = bit length) chip_i2s0_ctrl field values: sclkfreq = 0; sclk_inv = 0; dlen = 1; i2s_mode = 1; lralign = 1; lrpol = 0) figure 12. i2s port supported formats
sgtl5000 ea2 ds-0-3 35 sgtl5000 datasheet pcm format a signifies the data word beginning one sclk bit following the i2s_lrclk transition, as in i2s mode. pcm format b signifies the data word begin- ning after the i2s_lrclk transition, as in left justified. in slave mode, the pulse width of the i2s_lrclk does not matter. the pulse can range from one cycle high to all but one cycle high. in master mode, it will be driven one cycle high. figure 13 shows a functional drawing of t he different formats in master mode. 5.9. digital audio processing the sgtl5000 contains a digital audio processing block (dap) attached to the source select switch. the digitized signal from the source se lect switch can be routed into the dap block for audio processing. the dap has the following 5 sub blocks: ? dual input mixer ? sigmatel surround ? sigmatel bass enhancement ? 7-band paramter eq / 5-band graphic eq / tone control (only one can be used at a time) ? automatic volume control (avc) l n l (n-1) l 0 r n r (n-1) r 0 i2s_lrclk i2s_sclk i2s_din, dout pcm format a chip_i2s0_ctrl = 0x01f4 (sclkfreq = 1; ms = 1; sclk_inv = 1; dlen = 3; i2s_mode = 2; lralign = 0) l n l (n-1) l 0 r n r (n-1) r 0 r 1 r 1 l n l (n-1) l 0 r n r (n-1) r 0 i2s_lrclk i2s_sclk i2s_din, dout pcm format b chip_i2s0_ctrl = 0x01f6 (sclkfreq = 1; ms = 1; sclk_inv = 1; dlen = 3; i2s_mode = 2; lralign = 1) l n l (n-1) l 0 r n r (n-1) r 0 figure 13. pcm formats
36 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet the block diagram in figure 14 shows the sequence in which the signal passes through these blocks. when the dap block is added in the route, it must be enabled separately to get audio through. it is recommended to mute the outputs before enabling/disabling the dap block to avoid any pops or clicks due to discontinuities in the output. refer to section 6.2.4 for programming examples on how to enable/disable the dap block. each sub-block of the dap can be individu ally disabled if its processing is not required. the sections below describes the dap sub-blocks and how to configure them. 5.9.1. dual input mixer the dual input digital mixer allows for two incoming streams from the source select switch as shown in figure 15. automatic volume control (avc) sigmatel surround sigmatel bass enhance 7-band parametric eq 5-band graphic eq tone control from source select swtich to source select swtich dual input mixer set dap_control->dap_en to enable dap block only one of peq/geq/tc can be used at a time each dap sub-block can be configured in a pass -through mode main input mix input figure 14. digital audio processing block diagram
sgtl5000 ea2 ds-0-3 37 sgtl5000 datasheet figure 15. dap - dual input mixer the dual input mixer can be enabled or co nfigured in a pass-through mode (main channel will be passed throu gh without any mixing). wh en enabled, the volume of the main and mix channels can be independently controlled before they are mixed together. the volume range allowed on each channel is 0% to 200% of the incoming signal level. the default is 100% (same as input signal level) volume on the main input and 0% (muted) on the mix input. please refer to section 6.2.4.1 for program ming examples on how to enable/disable the mixer and also to set the main and mix channel volume. 5.9.2. sigmatel surround sigmatel surround is a royalty free virt ual surround algorithm for stereo or mono inputs. it widens and deepens sound stage for music input. the sgtl surround can be enabled or configured in pass-through mode (input will be passed through without any processing). when enabling the surround, mono or stereo input type must be selected based on the input signal. surround width may be adjusted for the size of the sound stage. main channel main channel volume dap_main_chan->vol mix channel volume dap_mix_chan->vol sum mixer output from source select switch from source select switch mix channel to sgtl surround block sigmatel surround dap_sgtl_surround -> width_control ->select input from dual mixer output to sgtl bass enhance
38 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet please refer to section 6.2.4.2 and section 6.3.5 for a programming example on how to configure surround width and how to enable/disable surround. 5.9.3. sigmatel bass enhance sigmatel bass enhance is a royalty-free algorithm that enhances natural bass response of the audio. bass enhance extracts bass content from right and left channels, adds bass and mixes this back up with the original signal. an optional complementary high pass filter is provided after the mixer. figure 16. dap- sigmatel bass enhance the sgtl bass enhance can be enabled or configured in pass-through mode ( input will be passed through without any processing). the cut-off frequency of the low-pass f ilter (lpf) can be selected based on the speakers freqeuncy response. the cut-off frequency of the low-pass and high-pass filters are selectable between 80hz to 225hz. also, the input signal and bass enhanced signal can be individually adjusted for level before the two signals are mixed. please refer to section 6.2.4.3 and section 6.3.6 for a programming example on how to configure bass enhance and ho w to enable/disable this feature. 5.9.4. 7-band parametric eq / 5-band graphic eq / tone control one 7-band parametric equalizer (peq) and one 5-band graphic equalizer (geq) and a tone control (bass and treble cont rol) blocks are implemented as mutually exclusive blocks. only one block can be used at a given time. please refer to section 6.2.4.4 for a progr amming example that shows how to select the desired eq mode. bass enhance low pass filter dap_bass_enhance ->cut_off dap_bass_enhance_ctrl ->bass _level dap_bass_enhance_ctrl ->lr_level input (from sgtl surround) high pass filter dap_bass _enhance_ctrl ->cutoff_hpf ->bypass _hpf output (to peq/geq/tc)
sgtl5000 ea2 ds-0-3 39 sgtl5000 datasheet 5.9.4.1. 7-band parametric eq the 7-band peq allows the designer to compensate for speaker response and to provide the ability to filter out resonant frequencies caused by the physical system design. the system designer can create custom eq presets such rock, speech, classical etc that allows the users the flexibility in customizing their audio. the 7-band peq is implemented using 7 casc aded second order iir filters. all fil- ters are implemented using programmable bi quad filters. figure 17 shows the trans- fer function and direct form 1 of th e five coefficient biquadratic filter. figure 17. 5-coefficient biquad filter and transfer function if a band is enabled but is not being used (flat response), then a value of 0.5 should be put in b 0 and all other coefficients should be set to 0.0. please note that the coef- ficients must be converted to hex values befor e writing to the registers. by default, all the filters are loaded with coeffi cients to give a flat response. in order to create eq presets such as rock, speech, classical etc, the coefficients must be calculated, converted to 20-bit hex va lues and written to the registers. note that coefficients are sample-rate dependent and separate coefficients must be gen- erated for different sample rates. please contact freescale for assistance with gen- erating the coefficients. 1 ? z 1 ? z 1 ? z 1 ? z x(z) h(z)x(z) b 0 b 1 b 2 -a 1 -a 2 2 2 1 1 2 2 1 1 0 1 ) ( ? ? ? ? + + + + = z a z a z b z b b z h direct form 1
40 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet please refer to section 6.3.2 for a programming example that shows how load the fil- ter coefficients when the end-user changes the preset. peq can be disabled (pass-through mode) by writing 0 to dap_audio_eq->en bits. 5.9.4.2. 5-band graphic eq the 5-band graphic equalizer is implemented using 5 parallel second order iir fil- ters. all filters are implemented using bi quad filters whose coefficients are pro- grammed to set the bands at specific frequency. the geq bands are fixed at 115hz, 330hz, 990hz, 3000hz, and 9900hz. the volume on each band is indepen- dently adjustable in the range of +12db to -11.75 db in 0.25db steps. please refer to section 6.3.3 for a programming example that shows how to change the geq volume 5.9.4.3. tone control tone control comprises treble and bass controls. the tone control is implemented as one 2nd order low pass filter (bass) and one 2nd order high pass filter (treble). please refer to section section 6.3.4 for a programming example that shows how to change bass and treble values. 5.9.5. automatic volume control (avc) an automatic volume control (avc) block is provided to reduce loud signals and amplify low level signals for easier liste ning. the avc is designed to compress audio when the measured level is above the programmed threshold or to expand the audio to the programmed threshold when the measured audio is below the threshold. the threshold level is programma ble with allowed range of 0db to -96 db. figure 18 shows the avc block diagram and controls. figure 18. dap avc block diagram threshold level compare volume control if < threshold decay (0.05db/s to ~200db/s) dap_avc_decay dap_avc_threshold -> max_gain if > threshold attack (0.8db/s to ~3200db/s) dap_avc_attack input from dual input mixer dap_avc_threshold output to sgtl surround
sgtl5000 ea2 ds-0-3 41 sgtl5000 datasheet when the measured audio level is below threshold, the avc can apply a maximum gain of up to 12db. the maximum gain can be selected, either 0, 6 or 12db. when the maximum gain is set to 0db the avc ac ts as a limiter. in this case the avc will only take effect when the signal level is above the threshold. the rate at which the incoming signal is attenuated down to the threshold is called the attack rate. too high of an attack will cause an unnatural so und as the input sig- nal is distorted. too low of an attack may cause saturation of the output as the incoming signal will not be compressed quickl y enough. the attack rate is program- mable with allowed range of 0.05db/s to 200db/s. when the signal is below the threshold, avc will adjust t he volume up until either the threshold or the maximum gain is reac hed. the rate at wh ich this volume is changed is called the decay rate. the decay rate is programmable with allowed range of 0.8db/s to 3200db/s. it is desira ble to use very slow decay rate to avoid any distortion in the signal and prevent the avc from entering a contiuous attack- decay loop. please refer to section 6.2.4.5 and sect ion 6.3.7 for a programming example that shows how to configure avc and how to enable/disable avc respectively. 5.10. control the sgtl5000 supports both i2c and spi control modes. the ctrl_mode pin chooses which mode will be used. when ctrl_mode is tied to ground, the con- trol mode is i2c. when ctrl_mode is tied to vddio, the control mode is spi. regardless of the mode, the co ntrol interface is used fo r all communication with the sgtl5000 including startup configuration, routing, volume, etc. 5.10.1. i2c the i2c port is implemented according to the i2c specification v2.0. the i2c inter- face is used to read and write all registers. for the 32qfn version of the sgtl5000, the i2c device address is 0n01010(r/w) where n is determined by i2c_adr0_cs and r/w is the read/write bit from the i2c protocol. for the 20qfn version of the sgtl5000 t he i2c address is always 0001010(r/w). the sgtl5000 is always the slave on all tr ansactions which means that an external master will always drive ctrl_clk. in general an i2c transaction looks as follows. all locations are accessed with a 16 bit address. each location is 16 bits wide. an example i2c write transaction follows: ? start condition ? device address with the r/w bit cleared to indicate write ? send two bytes for the 16 bit register address (most significant byte first)
42 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet ? send two bytes for the 16 bits of data to be written to the register (most signifi- cant byte first) ? stop condition an i2c read transaction is defined as follows: ? start condition ? device address with the r/w bit cleared to indicate write ? send two bytes for the 16 bit register address (most significant byte first) ? stop condition followed by start condition (or a single restart condition) ? device address with the r/w bit set to indicate read ? read two bytes from the addressed register (most significant byte first) ? stop condition figure 19 shows the functional i2c timing diagram. the protocol has an auto increment featur e. instead of sending the stop condition after two bytes of data, the master may continue to send data byte pairs for writing, or it may send extra clocks for reading da ta byte pairs. in either case, the access address is incremented after every two bytes of data. a start or stop condition from the i2c master interrupts the current command. for reads, unless a new address is written, a new start condition with r/w=0 re ads from the current address and contin- ues to auto increment. the following diagrams describe the different access formats. the gray fields are from the i2c master, and the white fields are the sgtl5000 responses. data[n] cor- responds to the data read from the address sent, data[n+1] is the data from the next register, and so on. s = start condition sr = restart condition a = ack n = nack p = stop condition ta2 silicon will allow for up to a 3.6v i2c si gnal level, regardless of the vddio level. table 13. write single location s device address w (0) a addr byte 1 a addr byte 0 a data byte 1 a data byte 0 a p i2c address a15 a8 a7 a0 d15 d 8 d7 d0 r/w ack ack ack ack ack start condition stop condition figure 19. functional i2c diagram
sgtl5000 ea2 ds-0-3 43 sgtl5000 datasheet table 14. write auto increment table 15. read single location table 16. read auto increment table 17. read continuing auto increment 5.10.2. spi serial peripheral interface (spi) is a co mmunications protocol supported by the sgtl5000. the sgtl5000 is always a slave. the ctrl_ad0_cs is used as the slave select (ss) when the master wants to select the sgtl5000 for communica- tion. ctrl_clk is conn ected to master?s sclk and ctrl_data is connected to master?s mosi line. the part only supports allows spi write operations and does not support read operations. figure 20 below shows the functional timing diagram of the spi communication pro- tocol as supported by sgtl5000 chip. note that on the rising edge of the ss, the chip latches to previous 32 bits of data. it interprets the latest 16-bits as register value and 16-bits preceding it as register address. figure 20. functional timing diagram of spi protocol s device address w (0) a start addr byte 1 a start addr byte 0 a data [n] byte 1 a data [n] byte 0 a data [n+1] byte 1 a data [n+1] byte 0 a p s device address w (0) a addr byte 1 a addr byte 0 a sr device address r (1) adata byte 1 adata byte 0 n p s device address w (0) a start addr byte 1 a start addr byte 0 a sr device address r (1) adata [n] byte 1 adata [n] byte 0 adata [n+1] byte 1 adata [n+1] byte 0 n p s device address ra data [n+2] byte 1 adata [n+2] byte 0 adata [n+3] byte 1 adata [n+3] byte 0 n p ss sck addr 15 addr 14 addr 8 addr 7 addr 6 addr 0 31 15 mosi val 15 val 14 val 8 val 7 val 6 val 0 23 70 16-bits register address 16-bits register value on rising edge of ss, latch the last 32 bits of data
44 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 6. programming examples this section provides programming examples that show how to configure the chip. the registers can be written/read by us ing i2c communication protocol. the chip also supports spi communication protocol but only register write operation is sup- ported. 6.1. prototype for readi ng and writing a register the generic register read write prot otype will be used throug hout this section as shown below. the i2c or sp i implementation will be sp ecific to the i2c/spi hard- ware used in the system. // this prototype writes a value to the entire register. all // bit-fields of the register will be written. write register registervalue // this prototype writes a value only to the bit-field specified. // in the actual implemention, the other bit-fields should be // masked to prevent them from being written. also, the // actual implementation should left-shift the bitfieldvalue // by appropriate number to match the starting bit location of // the bitfield. modify register -> bitfield, bitfieldvalue //bitfield location // example implementation // modify dap_en (bit 0) bit to value 1 to enable dap block modify( dap_control_reg, 0xfffe, 1 << dap_en_startbit ); // example implementation of modify void modify( unsigned short usregister, unsigned short usclearmask, unsigned short ussetvalue ) { unsigned short usdata; // 1) read current value readregister( usregister, &usdata ); // 2) clear out old bits usdata = usdata & usclearmask; // 3) set new bit values usdata = usdata | ussetvalue; // 4) write out new value created writeregister( usregister, usdata ); }
sgtl5000 ea2 ds-0-3 45 sgtl5000 datasheet 6.2. chip configuration all outputs (lineout, hp_out, i2s_out) are muted by default on powerup. to avoid any pops/clicks, the outputs should re main muted during these chip configura- tion steps. refer to section 6.2.6 for volume and mute control. 6.2.1. initialization 6.2.1.1. chip powerup and supply configurations after the power supp lies for chip is turned on, following initialization sequence should be followed. please note that ce rtain steps may be optional or different val- ues may need to be written based on the power supply voltage used and desired configuration. the initialization se quence below assumes vddio = 3.3v and vdda = 1.8v. //--------------- power supply configuration---------------- // note: this next 2 write calls is needed only if vddd is // internally driven by the chip // configure vddd level to 1.2v (bits 3:0) write chip_linreg_ctrl 0x0008 // power up internal linear regulator (set bit 9) write chip_ana_power 0x7260 // note: this next write call is needed only if vddd is // externally driven // turn off startup power supplies to save power (clear bit 12 and 13) write chip_ana_power 0x4260 // note: the next 2 write calls is needed only if both vdda and // vddio power supplies are less than 3.1v. // enable the internal oscillator for the charge pump (set bit 11) write chip_clk_top_ctrl 0x0800 // enable charge pump (set bit 11) write chip_ana_power 0x4a60 // note: the next 2 modify calls is only needed if both vdda and // vddio are greater than 3.1v // configure the chargepump to use the vddio rail (set bit 5 and bit 6) write chip_linreg_ctrl 0x006c //------ reference voltage and bias current configuration---------- // note: the value written in the next 2 write calls is dependent // on the vdda voltage value. // set ground, adc, dac reference voltage (bits 8:4). the value should // be set to vdda/2. this example assumes vdda = 1.8v. vdda/2 = 0.9v. // the bias current should be set to 50% of the nominal value (bits 3:1) write chip_ref_ctrl 0x004e // set lineout reference voltage to vddio/2 (1.65v) (bits 5:0) and bias cur- rent (bits 11:8) to the recommended value of 0.36ma for 10kohm load with 1nf capacitance write chip_line_out_ctrl 0x0322 //----------------other analog block configurations------------------ // configure slow ramp up rate to minimize pop (bit 0) write chip_ref_ctrl 0x004f // enable short detect mode for headphone left/right // and center channel and set short detect current trip level
46 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet // to 75ma write chip_short_ctrl 0x1106 // enable zero-cross detect if needed for hp_out (bit 5) and adc (bit 1) write chip_ana_ctrl 0x0133 //----------------power up inputs/outputs/digital blocks------------- // power up lineout, hp, adc, dac write chip_ana_power 0x6aff // power up desired digital blocks // i2s_in (bit 0), i2s_out (bit 1), dap (bit 4), dac (bit 5), // adc (bit 6) are powered on write chip_dig_power 0x0073 //--------------------set lineout volume level----------------------- // set the lineout volume level based on voltage reference (vag) // values using this formula // value = (int)(40*log(vag_val/lo_vagcntrl) + 15) // assuming vag_val and lo_vagcntrl is set to 0.9v and 1.65v respectively, the // left lo vol (bits 12:8) and right lo volume (bits 4:0) value should be set // to 5 write chip_line_out_vol 0x0505 6.2.1.2. system mclk and sample clock // configure sys_fs clock to 48khz // configure mclk_freq to 256*fs modify chip_clk_ctrl->sys_fs 0x0002 // bits 3:2 modify chip_clk_ctrl->mclk_freq 0x0000 // bits 1:0 // configure the i2s clocks in master mode // note: i2s lrclk is same as the system sample clock modify chip_i2s_ctrl->ms 0x0001 // bit 7 6.2.2. pll configuration these programming steps are needed only when the pll is used. please refer to section 5.4.2 for details on when to use the pll. to avoid any pops/clicks, the outputs should be muted during these chip configura- tion steps. refer to section 6.2.6 for volume and mute control. // power up the pll modify chip_ana_power->pll_powerup 0x0001 // bit 10 modify chip_ana_power->vcoamp_powerup 0x0001 // bit 8 // note: this step is required only when the external sys_mclk // is above 17mhz. in this case the external sys_mclk clock // must be divided by 2 modify chip_clk_top_ctrl->input_freq_div2 0x0001 // bit 3 sys_mclk_input_freq = sys_mclk_input_freq/2; // pll output frequency is different based on the sample clock // rate used. if (sys_fs_rate == 44.1khz) pll_output_freq = 180.6336mhz else pll_output_freq = 196.608mhz
sgtl5000 ea2 ds-0-3 47 sgtl5000 datasheet // set the pll dividers int_divisor = floor(pll_output_freq/sys_mclk_input_freq) frac_divisor = ((pll_output_freq/sys_mclk_input_freq) - int_divisor)*2048 modify chip_pll_ctrl->int_divisor int_divisor // bits 15:11 modify chip_pll_ctrl->frac_divisor frac_divisor // bits 10:0 6.2.3. input/output routing to avoid any pops/clicks, the outputs should be muted during these chip configura- tion steps. refer to section 6.2.6 for volume and mute control. a few example routes are shown below: // example 1: i2s_in -> dap -> dac -> lineout, hp_out // route i2s_in to dap modify chip_sss_ctrl->dap_select 0x0001 // bits 7:6 // route dap to dac modify chip_sss_ctrl->dac_select 0x0003 // bits 5:4 // select dac as the input to hp_out modify chip_ana_ctrl->select_hp 0x0000 // bit 6 // example 2: mic_in -> adc -> i2s_out // set adc input to mic_in modify chip_ana_ctrl->select_adc 0x0000 // bit 2 // route adc to i2s_out modify chip_sss_ctrl->i2s_select 0x0000 // bits 1:0 // example 3: linein -> hp_out // select linein as the input to hp_out modify chip_ana_ctrl->select_hp 0x0001 // bit 6 6.2.4. digital audio processor configuration to avoid any pops/clicks, the outputs should be muted during these chip configura- tion steps. refer to section 6.2.6 for volume and mute control. // enable dap block // note: dap will be in a pass-through mode if none of dap // sub-blocks are enabled. modify dap_control->dap_en 0x0001 // bit 0 6.2.4.1. dual input mixer these programming steps are needed only if dual input mixer feature is used. // enable dual input mixer modify dap_control->mix_en 0x0001 // bit 4 // note: this example assumes mix level of main and mix // channels as 100% and 50% respectively // configure main channel volume to 100% (no change from input // level)
48 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet write dap_main_chan 0x4000 // configure mix channel volume to 50% (attenuate the mix // input level by half) write dap_mix_chan 0x4000 6.2.4.2. sigmatel surround the sigmatel surround on/off function will be typically controlled by the end-user. end-user driven programming steps are shown in section 6.3. the default width_control of 4 should be appropriate for most applications. this optional programming step shows how to configure a different width value. // configure the surround width // (0x0 = least width, 0x7 = most width). this example shows // a width setting of 5 modify dap_sgtl_surround->width_control 0x0005 // bits 6:4 6.2.4.3. sigmatel bass enhance the sigmatel bass enhance on/off function will be typi cally controlled by the end- user. end-user driven programming steps are shown in section 6.3. the default lr_level value of 0x0005 results in no chan ge in the input signal level and bass_level value of 0x00 1f adds some harmonic bo ost to the main signal. the default settings should work for most applications. this optional programming step shows how to configure a different value. // gain up the input signal level modify dap_bass_enhance_ctrl->lr_level 0x0002 // bits 7:4 // add harmonic boost modify dap_bass_enhance_ctrl->bass_level 0x003f); // bits 6:0 6.2.4.4. 7-band parametric eq / 5-band graphic eq / tone control only one audio eq block can be used at a given time. the psuedocode in this sec- tion shows how to se lect each block. some parameters of the audio eq will typica lly be controlled by end-user. end-user driven programming steps are shown in section 6.3. // 7-band peq mode // select 7-band peq mode and enable 7 peq filters write dap_audio_eq 0x0001 write dap_peq 0x0007 // tone control mode write dap_audio_eq 0x0002 // 5-band geq mode write dap_audio_eq 0x0003
sgtl5000 ea2 ds-0-3 49 sgtl5000 datasheet 6.2.4.5. automatic volume control (avc) the avc on/off function will be typically cont rolled by the end-user . end-user driven programming steps are shown in section 6.3. the default configuration of the avc should work for most app lications. however, the following example shows how to change the configuration if needed. // configure threshold to -18db write dap_avc_threshold 0x0a40 // configure attack rate to 16db/s write dap_avc_attack 0x0014 // configure decay rate to 2db/s write dap_avc_decay 0x0028 6.2.5. i2s configuration by default the i2s port on the chip is configured for 24-bits of data in i2s format with sclk set for 64*fs. this can be modified by setting various bit-fields in chip_i2s_ctrl register. 6.2.6. volume control the outputs should be unmuted after all the configuration is complete. //---------------- input volume control--------------------- // configure adc left and right analog volume to desired default. // example shows volume of 0db write chip_ana_adc_ctrl 0x0000 // configure mic gain if needed. example shows gain of 20db modify chip_mic_ctrl->gain 0x0001 // bits 1:0 //---------------- volume and mute control--------------------- // configure hp_out left and right volume to minimum, unmute // hp_out and ramp the volume up to desired volume. write chip_ana_hp_ctrl 0x7f7f modify chip_ana_ctrl->mute_hp 0x0000 // bit 5 // code assumes that left and right volumes are set to same value // so it only uses the left volume for the calculations uscurrentvolleft = 0x7f; usnewvolleft = usnewvol & 0xff; usnumsteps = usnewvolleft - uscurrentvolleft; if (usnumsteps == 0) return; // ramp up for (int i = 0; i < usnumsteps; i++ ) { ++uscurrentvolleft; uscurrentvol = (uscurrentvolleft << 8) | (uscurrentvolleft); write chip_ana_hp_ctrl uscurrentvol; } // lineout and dac volume control modify chip_ana_ctrl->mute_lo 0x0000 // bit 8 // configure dac left and right digital volume. example shows // volume of 0db
50 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet write chip_dac_vol 0x3c3c modify chip_adcdac_ctrl->dac_mute_left 0x0000 // bit 2 modify chip_adcdac_ctrl->dac_mute_right 0x0000 // bit 3 // unmute adc modify chip_ana_ctrl->mute_adc 0x0000 // bit 0 6.3. end-user driven chip configuration end-users will control features like volume up/down, audio eq parameters such as bass and treble. this will require progra mming the chip with out introducing any pops/clicks or any disturbance to the output. this section shows examples on how to program these features. 6.3.1. volume and mute control refer to section 6.2.6 for examples on how to program volume when end-user changes the volume or mutes/unmutes outp ut. note that the dac volume ramp is automatically handled by the chip. 6.3.2. 7-band peq preset selection this programming example shows how to load the filter coefficients when the end- user changes peq presets such as rock, speech, classical etc. // load the 5 coefficients for each band and write them to // appropriate filter address. repeat this for all enabled // filters (this example shows 7 filters) for (i = 0; i < 7; i++) { // note that each 20-bit coefficient is broken into 16-bit msb // (unsigned short usxxmsb) and 4-bit lsb (unsigned short // usxxlsb) write dap_coef_wr_b0_lsb usb0msb[i] write dap_coef_wr_b0_msb usb0lsb[i] write dap_coef_wr_b1_lsb usb1msb[i] write dap_coef_wr_b1_msb usb1lsb[i] write dap_coef_wr_b2_lsb usb2msb[i] write dap_coef_wr_b2_msb usb2lsb[i] write dap_coef_wr_a1_lsb usa1msb[i] write dap_coef_wr_a1_msb usa1lsb[i] write dap_coef_wr_a2_lsb usa2msb[i] write dap_coef_wr_a2_msb usa2lsb[i] // set the index of the filter (bits 7:0) and load the // coeffiecents modify dap_filter_coef_access->index (0x0101 + i) // bit 8 } 6.3.3. 5-band geq volume change this programming example shows how to program the geq volume when end-user changes the volume on any of the 5 bands.
sgtl5000 ea2 ds-0-3 51 sgtl5000 datasheet geq volume should be ramped in 0.5 db steps in order to avoid any pops. the example assumes that volume is ramped on band 0. other bands can be pro- grammed similiarly. // read current volume set on band 0 uscurrentvol = read dap_audio_eq_bass_band0 // convert the new volume to hex value usnewvol = 4*dnewvoldb + 47; // calculate the number of steps usnumsteps = abs(usnewvol - uscurrentvol); if (usnumsteps == 0) return; for (int i = 0; i++; usnumsteps ) { if (usnewvol > uscurrentvol) ++uscurrentvol; else --uscurrentvol; write dap_audio_eq_bass_band0 uscurrentvol; } 6.3.4. tone control - bass and treble change this programming example shows how to program the tone control bass and tre- ble when end-user changes it on the fly. tone control bass and treble volume should be ramped in 0.5 db steps in order to avoid any pops. the example assumes that treble is changed to a new value. bass can be programmed similarly. // read current treble value uscurrentval = read dap_audio_eq_treble_band4 // convert the new treble value to hex value usnewval = 4*dnewvaldb + 47; // calculate the number of steps usnumsteps = abs(usnewval - uscurrentval); if (usnumsteps == 0) return; for (int i = 0; i++; usnumsteps ) { if (usnewval > uscurrentval) ++uscurrentval; else --uscurrentval; write dap_audio_eq_treble_band4 uscurrentval; } 6.3.5. sigmatel surround on/off this programming example shows how to program the surround when end-user turns it on/off on his device. the surround width should be ramped up to highest value before enabling/disabling the surround to avoid any pops.
52 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet // read current surround width value // width_control bits 6:4 usoriginalval = (read dap_sgtl_surround >> 4) && 0x0003; usnextval = usoriginalval; // ramp up the width to maximum value of 7 for (int i = 0; i++; (7 - usoriginalval) { ++usnextval; modify dap_sgtl_surround->width_control usnextval; } // enable (to disable, write 0x0000) surround // select bits 1:0 modify dap_sgtl_surround->select 0x0003; // ramp down the width to original value for (int i = 0; i++; (7 - usoriginalval) { --usnextval; modify dap_sgtl_surround->width_control usnextval; } 6.3.6. bass enhace on/off this programming example shows how to program the bass enhance on/off when end-user turns it on/off on his device. the bass level should be ramped down to the lowest bass before bass enhance feature is turned on/off. // read current bass level value // bass_level bits 6:0 usoriginalval = read dap_bass_enhance_ctrl && 0x007f; usnextval = usoriginalval; // ramp bass level to lowest bass (lowest bass = 0x007f) usnumsteps = abs(0x007f - usoriginalval); for (int i = 0; i++; usnumsteps ) { ++usnextval; modify dap_bass_enhance_ctrl->bass_level usnextval; } // enable (to disable, write 0x0000) bass enhance // en bit 0 modify dap_bass_enhance->en 0x0001; // ramp bass level back to original value for (int i = 0; i++; usnumsteps ) { --usnextval; modify dap_bass_enhance_ctrl->bass_level usnextval; }
sgtl5000 ea2 ds-0-3 53 sgtl5000 datasheet 6.3.7. automatic volume control (avc) on/off this programming example shows how to program the avc on/off when end-user turns it on/off on his device. // enable avc (to disable, write 0x0000) modify dap_avc_ctrl->en 0x0001 // bit 0
54 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7. register description 7.0.0.1. chip_id 0x0000 7.0.0.2. chip_dig_power 0x0002 1514131211109876543210 partid revid bits field rw reset definition 15:8 partid ro 0xa0 sgtl5000 part id 0xa0 - 8 bit identifier for sgtl5000 7:0 revid ro 0x00 sgtl5000 revision id 0xhh - revision number for sgtl5000. 1514131211109876543210 rsvd adc_powerup dac_powerup dap_powerup rsvd i2s_out_powerup i2s_in_powerup bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6 adc_powerup rw 0x0 enable/disable the adc block, both digital and analog 0x0 = disable 0x1 = enable 5 dac_powerup rw 0x0 enable/disable the dac block, both analog and digital 0x0 = disable 0x1 = enable 4 dap_powerup rw 0x0 enable/disable the dap block 0x0 = disable 0x1 = enable 3:2 rsvd rw 0x0 reserved 1 i2s_out_powe rup rw 0x0 enable/disable the i2s data output 0x0 = disable 0x1 = enable 0 i2s_in_poweru p rw 0x0 enable/disable the i2s data input 0x0 = disable 0x1 = enable
sgtl5000 ea2 ds-0-3 55 sgtl5000 datasheet 7.0.0.3. chip_clk_ctrl 0x0004 7.0.0.4. chip_i2s_ctrl 0x0006 1514131211109876543210 rsvd rate_mode sys_fs mclk_freq bits field rw reset definition 15:6 rsvd ro 0x0 reserved 5:4 rate_mode rw 0x0 sets the sample rate mode. mclk_freq is still specified relative to the rate in sys_fs 0x0 = sys_fs specifies the rate 0x1 = rate is 1/2 of the sys_fs rate 0x2 = rate is 1/4 of the sys_fs rate 0x3 = rate is 1/6 of the sys_fs rate 3:2 sys_fs rw 0x2 sets the internal system sample rate 0x0 = 32 khz 0x1 = 44.1 khz 0x2 = 48 khz 0x3 = 96 khz 1:0 mclk_freq rw 0x0 identifies incoming sys_mclk frequency and if the pll should be used 0x0 = 256*fs 0x1 = 384*fs 0x2 = 512*fs 0x3 = use pll the 0x3 (use pll) setting must be used if the sys_mclk is not a standard multiple of fs (256, 384 or 512). this setting can also be used if sys_mclk is a standard multiple of fs. before this field is set to 0x3 (use pll), the pll must be powered up by setting chip_ana_power- >pll_powerup and chip_ana_power- >vcoamp_powerup. also, the pll dividers must be calculated based on the external mclk rate and chip_pll_ctrl register must be set (see chip_pll_ctrl register description details on how to calculate the divisors). 1514131211109876543210 rsvd sclkfreq ms sclk_inv dlen i2s_mode lralign lrpol bits field rw reset definition 15:9 rsvd ro 0x0 reserved
56 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.5. chip_sss_ctrl 0x000a 8 sclkfreq rw 0x0 sets frequency of i2s_sclk when in master mode (ms=1). when in slave mode (ms=0), this field must be set appropriately to match sclk input rate. 0x0 = 64fs 0x1 = 32fs - not supported for rj mode (i2s_mode = 1) 7msrw 0x0 configures master or slave of i2s_lrclk and i2s_sclk. 0x0 = slave: i2s_lrclk and i2s_sclk are inputs 0x1 = master: i2s_lrclk and i2s_sclk are outputs note: if the pll is used (chip_clk_ctrl- >mclk_freq==0x3), the sgtl5000 must be a master of the i2s port (ms==1) 6sclk_invrw 0x0 sets the edge that data (input and output) is clocked in on for i2s_sclk 0x0 = data is valid on rising edge of i2s_sclk 0x1 = data is valid on falling edge of i2s_sclk 5:4 dlen rw 0x1 i2s data length 0x0 = 32 bits (only valid when sclkfreq=0), not valid for right justified mode 0x1 = 24 bits (only valid when sclkfreq=0) 0x2 = 20 bits 0x3 = 16 bits 3:2 i2s_mode rw 0x0 sets the mode for the i2s port 0x0 = i2s mode or left justified (use lralign to select) 0x1 = right justified mode 0x2 = pcm format a/b 0x3 = reserved 1lralignrw 0x0 i2s_lrclk alignment to data word. not used for right justified mode 0x0 = data word starts 1 i2s_sclk delay after i2s_lrclk transition (i2s format, pcm format a) 0x1 = data word starts afte r i2s_lrclk transition (left justified format, pcm format b) 0lrpolrw 0x0 i2s_lrclk polarity when data is presented. 0x0 = i2s_lrclk = 0 - left, 1 - right 1x0 = i2s_lrclk = 0 - right, 1 - left the left subframe should be presented first regardless of the setting of lrpol. 1514131211109876543210 rsvd dap_mix_lrswap dap_lrswap dac_lrswap rsvd i2s_lrswap dap_mix_select dap_select dac_select rsvd i2s_select bits field rw reset definition 15 rsvd rw 0x0 reserved bits field rw reset definition
sgtl5000 ea2 ds-0-3 57 sgtl5000 datasheet 7.0.0.6. chip_adcdac_ctrl 0x000e 14 dap_mix_lrsw ap rw 0x0 dap mixer input swap 0x0 = normal operation 0x1 = left and right channels for the dap mixer input will be swapped. 13 dap_lrswap rw 0x0 dap input swap 0x0 = normal operation 0x1 = left and right channels for the dap input will be swapped 12 dac_lrswap rw 0x0 dac input swap 0x0 = normal operation 0x1 = left and right channels for the dac will be swapped 11 rsvd rw 0x0 reserved 10 i2s_lrswap rw 0x0 i2s_dout swap 0x0 = normal operation 0x1 = left and right channels for the i2s_dout will be swapped 9:8 dap_mix_selec t rw 0x0 select data source for dap mixer 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = reserved 7:6 dap_select rw 0x0 select data source for dap 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = reserved 5:4 dac_select rw 0x1 select data source for dac 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = dap 3:2 rsvd rw 0x0 reserved 1:0 i2s_select wo 0x0 select data source for i2s_dout 0x0 = adc 0x1 = i2s_in 0x2 = reserved 0x3 = dap 1514131211109876543210 rsvd vol_busy_dac_right vol_busy_dac_left rsvd vol_ramp_en vol_expo_ramp rsvd dac_mute_right dac_mute_left adc_hpf_freeze adc_hpf_bypass bits field rw reset definition
58 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.7. chip_dac_vol 0x0010 bits field rw reset definition 15:14 rsvd ro 0x0 reserved 13 vol_busy_dac _right ro 0x0 volume busy dac right 0x0 = ready 0x1 = busy - this indicates the channel has not reached its programmed volume/mute level 12 vol_busy_dac _left ro 0x0 volume busy dac left 0x0 = ready 0x1 = busy - this indicates the channel has not reached its programmed volume/mute level 11:10 rsvd ro 0x0 reserved 9 vol_ramp_en rw 0x1 volume ramp enable 0x0 = disables volume ramp. new volume settings will take immediate effect without a ramp 0x1 = enables volume ramp this field affects dac_vol. the volume ramp effects both volume settings and mute. when set to 1 a soft mute is enabled. 8 vol_expo_ram p rw 0x0 exponential volume ramp enable 0x0 = linear ramp over top 4 volume octaves 0x1 = exponential ramp over full volume range this bit only takes effect if vol_ramp_en is 1. 7:4 rsvd rw 0x0 reserved 3 dac_mute_rig ht rw 0x1 dac right mute 0x0 = unmute 0x1 = muted if vol_ramp_en = 1, this is a soft mute. 2 dac_mute_lef t rw 0x1 dac left mute 0x0 = unmute 0x1 = muted if vol_ramp_en = 1, this is a soft mute. 1 adc_hpf_free ze rw 0x0 adc high pass filter freeze 0x0 = normal operation 0x1 = freeze the adc high-pass fi lter offset register. the offset will continue to be su btracted from the adc data stream. 0 adc_hpf_bypa ss rw 0x0 adc high pass filter bypass 0x0 = normal operation 0x1 = bypassed and offset not updated 1514131211109876543210 dac_vol_right dac_vol_left
sgtl5000 ea2 ds-0-3 59 sgtl5000 datasheet 7.0.0.8. chip_pad_strength 0x0014 bits field rw reset definition 15:8 dac_vol_righ t rw 0x3c dac right channel volume set the right channel dac volume with 0.5017 db steps from 0 to -90 db 0x3b and less = reserved 0x3c = 0 db 0x3d = -0.5 db 0xf0 = -90 db 0xfc and greater = muted if vol_ramp_en = 1, there will be an automatic ramp to the new volume setting. 7:0 dac_vol_left rw 0x3c dac left channel volume set the left channel dac volume with 0.5017 db steps from 0 to -90 db 0x3b and less = reserved 0x3c = 0 db 0x3d = -0.5 db 0xf0 = -90 db 0xfc and greater = muted if vol_ramp_en = 1, there will be an automatic ramp to the new volume setting. 1514131211109876543210 rsvd i2s_lrclk i2s_sclk i2s_dout ctrl_data ctrl_clk bits field rw reset definition 15:14 rsvd rw 0x0 reserved 9:8 i2s_lrclk rw 0x1 i2s lrclk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 7:6 i2s_sclk rw 0x1 i2s sclk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma
60 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.9. chip_ana_adc_ctrl 0x0020 5:4 i2s_dout rw 0x1 i2c dout pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 3:2 ctrl_data rw 0x3 i2c data pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 1:0 ctrl_clk rw 0x3 i2c clk pad drive strength sets drive strength for output pads per the table below. vddio 1.8v 2.5v 3.3v 0x0 = disable 0x1 = 1.66 ma 2.87 ma 4.02 ma 0x2 = 3.33 ma 5.74 ma 8.03 ma 0x3 = 4.99 ma 8.61 ma 12.05 ma 1514131211109876543210 rsvd adc_vol_m6db adc_vol_right adc_vol_left bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 adc_vol_m6db rw 0x0 adc volume range reduction this bit shifts both right and left analog adc volume range down by 6db. 0x0 = no change in adc range 0x1 = adc range reduced by 6db 7:4 adc_vol_righ t rw 0x0 adc right channel volume right channel analog adc volume control in 1.5db steps. 0x0 = 0db 0x1 = +1.5db ... 0xf = +22.5db this range will be -6db to +16.5db if adc_vol_m6db is set to 1. bits field rw reset definition
sgtl5000 ea2 ds-0-3 61 sgtl5000 datasheet 7.0.0.10. chip_ana_hp_ctrl 0x0022 7.0.0.11. chip_ana_ctrl 0x0024 this is an analog control register that in cludes mutes, input selects, and zero-cross- detectors for the adc, headphone, and lineout. 3:0 adc_vol_left rw 0x0 adc left channel volume left channel analog adc volume control in 1.5db steps. 0x0 = 0db 0x1 = +1.5db ... 0xf = +22.5db this range will be -6db to +16.5db if adc_vol_m6db is set to 1. 1514131211109876543210 rsvd hp_vol_right rsvd hp_vol_left bits field rw reset definition 15 rsvd ro 0x0 reserved 14:8 hp_vol_right rw 0x18 headphone right channel volume right channel headphone volume control with 0.5db steps. 0x00 = +12db 0x01 = +11.5db 0x18 = 0db ... 0x7f = -51.5db 7 rsvd ro 0x0 reserved 6:0 hp_vol_left rw 0x18 headphone left channel volume left channel headphone volume control with 0.5db steps. 0x00 = +12db 0x01 = +11.5db 0x18 = 0db ... 0x7f = -51.5db 1514131211109876543210 rsvd mute_lo rsvd select_hp en_zcd_hp mute_hp rsvd select_adc en_zcd_adc mute_adc bits field rw reset definition
62 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.12. chip_linreg_ctrl 0x0026 this register controls the vddd linear regulator and the charge pump. bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8 mute_lo rw 0x1 lineout mute 0x0 = unmute 0x1 = mute 7 rsvd ro 0x0 reserved 6 select_hp rw 0x0 select the headphone input. 0x0 = dac 0x1 = line in 5 en_zcd_hp rw 0x0 enable the headphone zero cross detector (zcd) 0x0 = hp zcd disabled 0x1 = hp zcd enabled 4 mute_hp rw 0x1 mute the headphone outputs 0x0 = unmute 0x1 = mute 3 rsvd ro 0x0 reserved 2 select_adc rw 0x0 select the adc input. 0x0 = microphone 0x1 = line in 1en_zcd_adcrw 0x0 enable the adc analog zero cross detector (zcd) 0x0 = adc zcd disabled 0x1 = adc zcd enabled 0 mute_adc rw 0x1 mute the adc analog volume 0x0 = unmute 0x1 = mute 1514131211109876543210 rsvd vddc_man_assn vddc_assn_ovrd rsvd d_programming bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6 vddc_man_ass n rw 0x0 determines chargepump so urce when vddc_assn_ovrd is set. 0x0 = vdda 0x1 = vddio
sgtl5000 ea2 ds-0-3 63 sgtl5000 datasheet 7.0.0.13. chip_ref_ctrl 0x0028 this register controls the bandgap reference bias voltage and currents. 5 vddc_assn_ov rd rw 0x0 chargepump source assignment override 0x0 = chargepump source is automatically assigned based on higher of vdda and vddio 0x1 = the source of chargepump is manually assigned by vddc_man_assn if vddio and vdda are both the same and greater than 3.1v, vddc_assn_ovrd and vddc_man_assn should be used to manually assign vddio as the source for chargepump. 4 rsvd rw 0x0 reserved 3:0 d_programmi ng rw 0x0 sets the vddd lin. regulator output voltage in 50mv steps. must clear pwd_linreg_d bit to enable this lin reg. 0x0=1.60 0xf=0.85 1514131211109876543210 rsvd vag_val bias_ctrl small_pop bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8:4 vag_val rw 0x0 analog ground voltage control these bits control the analog ground voltage in 25mv steps. this should usually be set to vdda/2 or lower for best performance (maximum output swi ng at minimum thd). this vag reference is also used for the dac and adc voltage reference. so changing this voltage scales the output swing of the dac and the out put signal of the adc. 0x00 = 0.800v 0x1f = 1.575v 3:1 bias_ctrl rw 0x0 bias control these bits adjust the bias currents for all of the analog blocks. by lowering the bias current a lower quiescent power is achieved. it should be noted that this mode can affect perfomance by 3-4db. 0x0 = nominal 0x1-0x3=+12.5% 0x4=-12.5% 0x5=-25% 0x6=-37.5% 0x7=-50% 0 small_pop rw 0x0 vag ramp control setting this bit slows down the vag ramp from ~200ms to ~400ms to reduce the startup pop, but increases the turn on/ off time. 0x0 = normal vag ramp 0x1 = slowdown vag ramp bits field rw reset definition
64 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.14. chip_mic_ctrl 0x002a this register controls the microphone ga in and the internal microphone biasing cir- cuitry. 7.0.0.15. chip_line_out_ctrl 0x002c 1514131211109876543210 rsvd bias_resistor rsvd bias_volt rsvd gain bits field rw reset definition 15:10 rsvd ro 0x0 reserved 9:8 bias_resistor rw 0x0 mic bias output impedance adjustment controls an adjustable output impedance for the microphone bias. if this is set to zero the micbias block is powered off and the output is highz. 0x0 = powered off 0x1 = 2kohm 0x2 = 4kohm 0x3 = 8kohm 7 rsvd ro 0x0 reserved 6:4 bias_volt rw 0x0 mic bias voltage adjustment controls an adjustable bias voltage for the microphone bias amp in 250mv steps. this bias voltage setting should be no more than vdda-200mv for adequa te power supply rejection. 0x0 = 1.25v ... 0x7 = 3.00v 3:2 rsvd ro 0x0 reserved 1:0 gain rw 0x0 mic amplifier gain sets the microphone amplifier gain. at 0db setting the thd can be slightly higher than other paths- typically around ~65db. at other gain settings the thd will be better. 0x0 = 0db 0x1 = +20db 0x2 = +30db 0x3 = +40db 1514131211109876543210 rsvd out_current rsvd lo_vagcntrl
sgtl5000 ea2 ds-0-3 65 sgtl5000 datasheet 7.0.0.16. chip_line_out_vol 0x002e bits field rw reset definition 15:12 rsvd ro 0x0 reserved 11:8 out_current rw 0x0 controls the output bias current for the lineout amplifiers. the nominal recommended setting for a 10kohm load with 1nf load cap is 0x3. ther e are only 5 valid settings. 0x0=0.18ma, 0x1=0.27ma, 0x 3=0.36ma, 0x7=0.45ma, 0xf=0.54ma 7:6 rsvd ro 0x0 reserved 5:0 lo_vagcntrl rw 0x0 lineout amplifier analog ground voltage controls the analog ground voltage for the lineout amplifiers in 25mv steps. this should usually be set to vddio/2. 0x00 = 0.800v ... 0x1f = 1.575v ... 0x23 = 1.675 0x24-0x3f are invalid 1514131211109876543210 rsvd lo_vol_right rsvd lo_vol_left bits field rw reset definition 15:13 rsvd ro 0x0 reserved 12:8 lo_vol_right rw 0x4 lineout right channel volume controls the right channel lineo ut volume in 0.5db steps. higher codes have more attenuation. see programming information for left channel. 7:5 rsvd ro 0x0 reserved 4:0 lo_vol_left rw 0x4 lineout left channel output level the lo_vol_left is used to normalize the output level of the left line output to full scale based on the values used to set line_out_ctrl -> lo_vagcntrl and chip_ref_ctrl -> vag_val. in general th is field should be set to: 40*log(( vag_val )/ (lo_vagcntrl) ) + 15 table 18 shows suggested values based on typical vddio and vdda voltages. after setting to the nominal voltage, this field can be used to adjust the output level in +/-. 5db increments by using values higher or lower than the nominal setting.
66 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.17. chip_ana_power 0x0030 this register contains all of the powerdow n controls for the analog blocks. the only other powerdown controls are bias_resist or in the mic_ctrl register and the en_zcd control bits in ana_ctrl. table 18. line out output level values vdda vag_val vddio lo_vagcntrl lo_vol_* 1.8v 0.9 3.3v 1.55 0x06 1.8v 0.9 1.8v 0.9 0x0f 3.3v 1.55 1.8v 0.9 0x19 3.3v 1.55 3.3v 1.55 0x0f 1514131211109876543210 rsvd dac_mono linreg_simple_powerup startup_powerup vddc_chrgpmp_powerup pll_powerup linreg_d_powerup vcoamp_powerup vag_powerup adc_mono reftop_powerup headphone_powerup dac_powerup capless_headphone_powerup adc_powerup lineout_powerup bits field rw reset definition 15 rsvd rw 0x0 reserved 14 dac_mono rw 0x1 while dac_powerup is set, this allows the dac to be put into left only mono operation for power savings. 0x0 = mono (left only) 0x1 = stereo 13 linreg_simple _powerup rw 0x1 power up the simple (low power) digital supply regulator. after reset, this bit can be cleared if vddd is driven externally or the primary digital linreg is enabled with linreg_d_powerup 0x0 = power down 0x1 = power up 12 startup_powe rup rw 0x1 power up the circuitry needed during the power up ramp and reset. after reset this bit can be cleared if vddd is coming from an external source. 0x0 = power down 0x1 = power up
sgtl5000 ea2 ds-0-3 67 sgtl5000 datasheet 11 vddc_chrgpm p_powerup rw 0x0 power up the vddc chargepump block. if neither vdda or vddio is 3v or larger this bit should be cleared before analog blocks are powered up. 0x0 = power down 0x1 = power up note that for charge pump to f unction, either the pll must be powered on and programmed correctly (refer to chip_clk_ctrl->mclk_freq description) or the internal oscillator (set clk_top_ct rl->enable_int_osc) must be enabled 10 pll_powerup rw 0x0 pll power up 0x0 = power down 0x1 = power up when cleared, the pll will be turned off. this must be set before chip_clk_ctrl -> mclk_freq is programmed to 0x3. the chip_pll_ctrl register must be configured correctly before setting this bit. 9 linreg_d_pow erup rw 0x0 power up the primary vddd linear regulator. 0x0 = power down 0x1 = power up 8 vcoamp_powe rup rw 0x0 power up the pll vco amplifier. 0x0 = power down 0x1 = power up 7 vag_powerup rw 0x0 power up the vag reference buffer. setting this bit starts the power up ramp for the headphone and lineout. the headphone (and/or lineout) powerup should be set before clearing this bit. when this bit is cleared the powerdown ramp is started. the headphone (and/or lineout) powerup should stay set until the vag is fully ramped down (200-400ms after clearing this bit). 0x0 = power down 0x1 = power up 6 adc_mono rw 0x1 while adc_powerup is set, this allows the adc to be put into left only mono operation for power savings. this mode is useful when only using the microphone input. 0x0 = mono (left only) 0x1 = stereo 5 reftop_powe rup rw 0x1 power up the reference bias currents 0x0 = power down 0x1 = power up this bit can be cleared when the part is is a sleep state to minimize analog power. 4 headphone_p owerup rw 0x0 power up the headphone amplifiers 0x0 = power down 0x1 = power up 3 dac_powerup rw 0x0 power up the dacs 0x0 = power down 0x1 = power up 2 capless_head phone_power up rw 0x0 power up the capless headphone mode 0x0 = power down 0x1 = power up bits field rw reset definition
68 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.18. chip_pll_ctrl 0x0032 this register may only be changed after reset, and before pll_powerup is set. 1 adc_powerup rw 0x0 power up the adcs 0x0 = power down 0x1 = power up 0lineout_powe rup rw 0x0 power up the lineout amplifiers 0x0 = power down 0x1 = power up 1514131211109876543210 int_divisor frac_divisor bits field rw reset definition 15:11 int_divisor rw 0xa this is the integer portion of the pll divisor. to determine the value of this field, use the following calculation: int_divisor = floor(pll_output_freq/ input_freq) pll_output_freq = 180.6336 mh z if system sample rate = 44.1 khz else pll_output_freq = 196.608 mhz if system sample rate != 44.1 khz input_freq = frequency of the external mclk provided if chip_clk_top_ctrl->input_freq_div2 = 0x0 else input_freq = (frequency of the external mclk provided/2) if chip_clk_top_ctrl->input_freq_div2 = 0x1 10:0 frac_divisor rw 0x0 this is the fractional portion of the pll divisor. to determine the value of this field, use the following calculation: frac_divisor = ((pll_out put_freq/input_freq) - int_divisor)*2048 pll_output_freq = 180.6336 mh z if system sample rate = 44.1 khz else pll_output_freq = 196.608 mhz if system sample rate != 44.1 khz input_freq = frequency of the external mclk provided if chip_clk_top_ctrl->input_freq_div2 = 0x0 else input_freq = (frequency of the external mclk provided/2) if chip_clk_top_ctrl->input_freq_div2 = 0x1 bits field rw reset definition
sgtl5000 ea2 ds-0-3 69 sgtl5000 datasheet 7.0.0.19. chip_clk_top_ctrl 0x0034 miscellaneous controls for the clock block. 7.0.0.20. chip_ana_status 0x0036 status bits for analog blocks. 1514131211109876543210 rsvd enable_int_osc rsvd input_freq_div2 rsvd bits field rw reset definition 15:12 reserved ro 0x0 reserved 11 enable_int_os c rw 0x0 setting this bit enables an internal oscillator to be used for the zero cross detectors, the s hort detect recovery, and the charge pump. this will allow the i2s clock to be shut off while still operating an analog signal path. this bit can be kept on when the i2s clock is enabled, but the i2s clock is more accurate so it is preferred to clear this bit when i2s is present. 10:4 rsvd rw 0x0 reserved 3 input_freq_di v2 rw 0x0 sys_mclk divider before pll input 0x0 = pass through 0x1 = sys_mclk is divided by 2 before entering pll this must be set when the input clock is above 17mhz. this has no effect when the pll is powered down. 2:0 rsvd rw 0x0 reserved 1514131211109876543210 rsvd lrshort_sts cshort_sts rsvd pll_is_locked rsvd bits field rw reset definition 15:10 rsvd ro 0x0 reserved 9 lrshort_sts ro 0x0 this bit is high whenever a shor t is detected on the left or right channel headphone drivers. 0x0 = normal 0x1 = short detected 8 cshort_sts ro 0x0 this bit is high whenever a short is detected on the capless headphone common/center channel driver. 0x0 = normal 0x1 = short detected 7:5 rsvd ro 0x0 reserved
70 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.21. chip_ana_test1 0x0038 these register controls are intended only for debug. 4 pll_is_locked ro 0x0 this bit goes high after the pll is locked. 0x0 = pll is not locked 0x1 = pll is locked 3:0 rsvd ro 0x0 reserved 1514131211109876543210 hp_iall_adj hp_i1_adj hp_antipop hp_classab hp_hold_gnd_center hp_hold_gnd vag_doub_current vag_classa tm_adcin_tohp tm_hpcommon tm_select_mic testmode bits field rw reset definition 15:14 hp_iall_adj rw 0x0 these bits control the overal l bias current of the headphone amplifier (all stages including first and output stage). 0x0=nominal, 0x1=-50%, 0x2=+50%, 0x3=-40% 13:12 hp_i1_adj rw 0x0 these bits control the bias cu rrent for the first stage of the headphone amplifier. 0x0=nominal, 0x1=-50%, 0x2=+100%, 0x3=+50% 11:9 hp_antipop rw 0x0 these bits control the headphone output current in classa mode and also the pulldown strength while powering off. these bits will normally not be needed. 8 hp_classab rw 0x1 this defaults high. when this bit is high the headphone is in classab mode. classa mode would normally not be used. 7 hp_hold_gnd_ center rw 0x1 this defaults high. when this bit is high and the capless headphone center channel is powered off the output will be tied to ground. this is the preferred mode of operation for best antipop performance. 6 hp_hold_gnd rw 0x1 this defaults high. when this bit is high and the headphone is powered off the output will be ti ed to ground. this is the preferred mode of operation for best antipop performance. 5 vag_doub_cur rent rw 0x0 double the vag output current when in classa mode. 4 vag_classa rw 0x0 turn off the classab output current for the vag buffer. the classa current is limited so th is may cause clipping in some modes. 3tm_adcin_toh p rw 0x0 put adcmux output onto th e headphone output pin. must remove headphone load and any external headphone compensation for this mode. 2 tm_hpcommon rw 0x0 enable headphone common to be used in adcmux for testing 1 tm_select_mi c rw 0x0 enable the mic-adc-dac-hp path bits field rw reset definition
sgtl5000 ea2 ds-0-3 71 sgtl5000 datasheet 7.0.0.22. chip_ana_test2 0x003a 0 testmode rw 0x0 enable the analog testmode paths 1514131211109876543210 rsvd lineout_to_vdda spare monomode_dac vco_tune_again lo_pass_mastervag invert_dac_sample_clock invert_dac_data_timing dac_extend_rtz dac_double_i dac_dis_rtz dac_classa invert_adc_sample_clock invert_adc_data_timing adc_lessi adc_ditheroff bits field rw reset definition 15 rsvd ro 0x0 reserved 14 lineout_to_vd da rw 0x0 changes the lineout amplifier power supply from vddio to vdda. typically lineout should be on the higher power supply. this bit is useful when vdda is ~3.3v and vddio is ~1.8v. 13 spare rw 0x0 spare registers to analog. 12 monomode_da c rw 0x0 copy the left channel dac data to the right channel. this allows both left and right to play from mono dac data. 11 vco_tune_aga in rw 0x0 when toggled high then low forces the pll vco to retune the number of inverters in the ring oscillator loop. 10 lo_pass_mast ervag rw 0x0 tie the main analog vag to the lineout vag. this can improve snr for the lineout when both are the same voltage. 9 invert_dac_sa mple_clock rw 0x0 change the clock edge used for the dac output sampling. 8 invert_dac_d ata_timing rw 0x0 change the clock edge used for the digital to analog dac data crossing. 7 dac_extend_r tz rw 0x0 extend the return-to-zero time for the dac. 6 dac_double_i rw 0x0 double the output current of the dac amplifier when it is in classa mode. 5 dac_dis_rtz rw 0x0 turn off the return-to-zero in the dac. in mode cases this will hurt the sndr of the dac. 4 dac_classa rw 0x0 turn off the classab mode in the dac amplifier. this mode should normally not be used. the output current will not be high enough to support a full scale signal in this mode. 3 invert_adc_sa mple_clock rw 0x0 change the clock edge used for the adc sampling. 2 invert_adc_d ata_timing rw 0x0 change the clock edge used for the analog to digital adc data crossing 1 adc_lessi rw 0x0 drops adc bias currents by 20% bits field rw reset definition
72 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.23. chip_short_ctrl 0x003c this register contains controls for the headphone short detectors. 0 adc_ditherof f rw 0x0 turns off the adc dithering. 1514131211109876543210 rsvd lvladjr rsvd lvladjl rsvd lvladjc mode_lr mode_cm bits field rw reset definition 15 rsvd ro 0x0 reserved 14:12 lvladjr rw 0x0 these bits adjust the sens itivity of the right channel headphone short detector in 25ma steps.this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short detect trip point is also effected by the bias current adjustments made by chip_ref_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=25ma 0x2=50ma 0x1=75ma 0x0=100ma 0x4=125ma 0x5=150ma 0x6=175ma 0x7=200ma 11 rsvd ro 0x0 reserved 10:8 lvladjl rw 0x0 these bits adjust the sensitivity of the left channel headphone short detector in 25ma steps.this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short detect trip point is also effected by the bias current adjustments made by chip_re f_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=25ma 0x2=50ma 0x1=75ma 0x0=100ma 0x4=125ma 0x5=150ma 0x6=175ma 0x7=200ma 7 rsvd ro 0x0 reserved bits field rw reset definition
sgtl5000 ea2 ds-0-3 73 sgtl5000 datasheet 6:4 lvladjc rw 0x0 these bits adjust the sensit ivity of the capless headphone center channel short detector in 50ma steps. this trip point can vary by ~30% over process so leave plenty of guardband to avoid false trips. this short de tect trip point is also effected by the bias current adjustments chip_ref_ctrl -> bias_ctrl and by chip_ana_test1 -> hp_iall_adj. 0x3=50ma 0x2=100ma 0x1=150ma 0x0=200ma 0x4=250ma 0x5=300ma 0x6=350ma 0x7=400ma 3:2 mode_lr rw 0x0 these bits control the behavior of the short detector for the capless headphone central channel driver. this mode should be set prior to powering up the headphone amplifier. when a short is detected the amplifier ou tput switches to classa mode interally to avoid excessive currents. 0x0 = disable short detector, reset short detect latch, software view non-latched short signal 0x1 = enable short detector and reset the latch at timeout (every ~50ms) 0x2 = this mode is not used/invalid 0x3 = enable short detector with only manual reset (have to return to 0x0 to reset the latch) 1:0 mode_cm rw 0x0 these bits control the behavior of the short detector for the capless headphone central channel driver. this mode should be set prior to powering up the headphone amplifier. when a short is detected the amplifier ou tput switches to classa mode interally to avoid excessive currents. 0x0 = disable short detector, reset short detect latch, software view non-latched short signal 0x1 = enable short detector and reset the latch at timeout (every ~50ms) 0x2 = enable short detector and auto reset when output voltage rises (preferred mode) 0x3 = enable short detector with only manual reset (have to return to 0x0 to reset the latch) bits field rw reset definition
74 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.24. dap_control 0x0100 7.0.0.25. dap_peq 0x0102 7.0.0.26. dap_bass_enhance 0x0104 1514131211109876543210 rsvd mix_en rsvd dap_en bits field rw reset definition 15:5 rsvd ro 0x0 reserved 4mix_enrw 0x0 enable/disable the dap mixer path 0x0 = disable 0x1 = enable when enabled, dap_en must also be enabled to use the mixer. 3:1 rsvd ro 0x0 reserved 0 dap_en rw 0x0 enable/disable digital audio processing (dap) 0x0 = disable. when disabled, no audio will pass-through. 0x1 = enable. when enabled, audio can pass-through dap even if none of the dap functions are enabled. 1514131211109876543210 rsvd en bits field rw reset definition 15:3 rsvd ro 0x0 reserved 2:0 en rw 0x0 set to enable the peq filters 0x0 = disabled 0x1 = 1 filter enabled 0x2 = 2 filters enabled ..... 0x7 = cascaded 7 filters dap_audio_eq->en bit must be set to 1 in order to enable the peq 1514131211109876543210 rsvd bypass_hpf rsvd cutoff rsvd en bits field rw reset definition 15:9 rsvd ro 0x0 reserved
sgtl5000 ea2 ds-0-3 75 sgtl5000 datasheet 7.0.0.27. dap_bass_enhance_ctrl 0x0106 7.0.0.28. dap_audio_eq 0x0108 8 bypass_hpf rw 0x0 bypass high pass filter 0x0 = enable high pass filter 0x1 = bypass high pass filter 7 rsvd ro 0x0 reserved 6:4 cutoff rw 0x4 set cut-off frequency 0x0 = 80 hz 0x1 = 100 hz 0x2 = 125 hz 0x3 = 150 hz 0x4 = 175 hz 0x5 = 200 hz 0x6 = 225 hz 3:1 rsvd ro 0x0 reserved 0enrw 0x0 enable/disable bass enhance 0x0 = disable 0x1 = enable 1514131211109876543210 rsvd lr_level rsvd bass_level bits field rw reset definition 15:14 rsvd ro 0x0 reserved 13:8 lr_level rw 0x5 left/right mix level control 0x00= +6db for main channel ...... 0x3f= least l/r channel level 7 rsvd ro 0x0 6:0 bass_level rw 0x1f bass harmonic level control 0x00= most harmonic boost ...... 0x7f=least harmonic boost 1514131211109876543210 rsvd en bits field rw reset definition 15:2 rsvd ro 0x0 reserved bits field rw reset definition
76 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.29. dap_sgtl_surround 0x010a 7.0.0.30. dap_filter_coef_access 0x010c 1:0 en rw 0x0 selects between peq/geq/tone control and enables it. 0x0 = disabled. 0x1 = enable peq. note: dap_peq->en bit must also be set to the desired number of filters (bands) in order for the peq to be enabled. 0x2 = enable tone control 0x3 = enable 5 band geq 1514131211109876543210 rsvd width_control rsvd select bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:4 width_contro l rw 0x4 sgtl surround width control - the width control changes the perceived width of the sound field. 0x0 = least width ...... 0x7 = most width 3:2 rsvd ro 0x0 reserved 1:0 select rw 0x0 sgtl surround selection 0x0 = disabled 0x1 = disabled 0x2 = mono input enable 0x3 = stereo input enable 1514131211109876543210 rsvd wr index bits field rw reset definition 15:9 rsvd ro 0x0 reserved 8wrwo 0x0 when set, the coefficients written in the ten coefficient data registers will be loaded into t he filter specified by index bits field rw reset definition
sgtl5000 ea2 ds-0-3 77 sgtl5000 datasheet 7.0.0.31. dap_coef_wr_b0_msb 0x010e 7:0 index rw 0x0 specifies the index for each of the seven bands of the filter coefficient that needs to be written to. each filter has 5 coefficients that need to be loaded into the 10 coefficient registers (msb,lsb) before se tting the index and wr bit. steps to write coefficients: 1. write the five 20-bit coefficient values to dap_coef_wr_xx_msb and dap_coef_wr_xx_lsb registers (xx= b0,b1,b2,a1,a2) 2. set index of the coefficient from the table below. 3. set the wr bit to load the coefficient. note: steps 2 and 3 can be performed with a single write to dap_filter_coef_access register. coefficient address: band 0 = 0x00 band 1 = 0x01 band 2 = 0x02 band 3 = 0x03 band 4 = 0x04 ... band 7 = 0x06 1514131211109876543210 bit_19 bit_18 bit_17 bit_16 bit_15 bit_14 bit_13 bit_12 bit_11 bit_10 bit_9 bit_8 bit_7 bit_6 bit_5 bit_4 bits field rw reset definition 15 bit_19 wo 0x0 most significant 16-bits of the 20 -bit filter coefficient that needs to be written 14 bit_18 wo 0x0 13 bit_17 wo 0x0 12 bit_16 wo 0x0 11 bit_15 wo 0x0 10 bit_14 wo 0x0 9bit_13wo 0x0 8bit_12wo 0x0 7bit_11wo 0x0 6bit_10wo 0x0 5bit_9wo 0x0 4bit_8wo 0x0 3bit_7wo 0x0 2bit_6wo 0x0 1bit_5wo 0x0 bits field rw reset definition
78 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.32. dap_coef_wr_b0_lsb 0x0110 7.0.0.33. dap_audio_eq_bass_ba nd0 0x0116 115hz 7.0.0.34. dap_audio_eq_band1 0x0118 330hz 0bit_4wo 0x0 1514131211109876543210 rsvd bit_3 bit_2 bit_1 bit_0 bits field rw reset definition 15:4 rsvd ro 0x0 3bit_3wo 0x0 2bit_2wo 0x0 1bit_1wo 0x0 0bit_0wo 0x0 least significant 4 bits of the 20 -bit filter coefficient that needs to be written. 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets tone control bass/geq band0 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved bits field rw reset definition
sgtl5000 ea2 ds-0-3 79 sgtl5000 datasheet 7.0.0.35. dap_audio_eq_band2 0x011a 990hz 7.0.0.36. dap_audio_eq_band3 0x011c 3000hz 7.0.0.37. dap_audio_eq_treble_band4 0x011e 9900hz 6:0 volume rw 0x2f sets geq band1 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets geq band2 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets geq band3 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 rsvd volume bits field rw reset definition
80 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.38. dap_main_chan 0x0120 sets the main channel volume level. 7.0.0.39. dap_mix_chan 0x0122 sets the mix channel volume level. 7.0.0.40. dap_avc_ctrl 0x0124 bits field rw reset definition 15:7 rsvd ro 0x0 reserved 6:0 volume rw 0x2f sets tone control treble/geq band4 0x5f = sets to 12db 0x2f = sets to 0db 0x00 = sets to -12db each lsb is 0.25db. to convert db to hex value, use: hex value = 4*dbvalue + 47 1514131211109876543210 vol bits field rw reset definition 15:0 vol rw 0x8000 dap main channel volume 0xffff = 200% 0x8000 (default) = 100% 0x0000 = 0% 1514131211109876543210 vol bits field rw reset definition 15:0 vol rw 0x0000 dap mix channel volume 0xffff = 200% 0x8000 = 100% 0x0000 (default) = 0% 1514131211109876543210 rsvd rsvd max_gain rsvd lbi_response rsvd hard_limit_en rsvd en bits field rw reset definition 15 rsvd ro 0x0 reserved 14 rsvd rw 0x1 reserved.
sgtl5000 ea2 ds-0-3 81 sgtl5000 datasheet 7.0.0.41. dap_avc_threshold 0x0126 7.0.0.42. dap_avc_attack 0x0128 13:12 max_gain rw 0x1 maximum gain that can be applied by the avc in expander mode. 0x0 = 0db gain 0x1 = 6db of gain 0x2 = 12db of gain 11:10 rsvd ro 0x0 reserved 9:8 lbi_response rw 0x1 integrator response 0x0 = 0ms lbi 0x1 = 25ms lbi 0x2 = 50ms lbi 0x3 = 100ms lbi 7:6 rsvd ro 0x0 reserved 5 hard_limit_en rw 0x0 enable hard limiter mode 0x0 = hard limit disabled. avc compressor/expander is enabled. 0x1 = hard limit enabled. the signal is limited to the programmed threshold. (signal saturates at the threshold) 4:1 rsvd ro 0x0 reserved 0enrw 0x0 enable/disable avc 0x0 = disable 0x1 = enable 1514131211109876543210 thresh bits field rw reset definition 15:0 thresh rw 0x1473 avc threshold value threshold is programmable. use the following formula to calculate hex value: hex value = ((10^(threshold_db/20))*0.636)*2^15 threshold can be set in the range of 0db to -96 db example values: 0x1473 = set threshold to -12db 0x0a40 = set threshold to -18db 1514131211109876543210 rsvd rate bits field rw reset definition 15:12 rsvd ro 0x0 reserved bits field rw reset definition
82 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.43. dap_avc_decay 0x012a 7.0.0.44. dap_coef_wr_b1_msb 0x012c 11:0 rate rw 0x28 avc attack rate this is the rate at which the avc will apply attenuation to the signal to bring it to the threshold level. avc attack rate is programmable. to use a custom rate, use the formula below to convert from db/s to hex value: hex value = (1 - (10^(-(rate_dbs/( 20*sys_fs)))) * 2^19 where, sys_fs is the system sa mple rate co nfigured in chip_clk_ctrl register. example values: 0x28 = 32db/s 0x10 = 8db/s 0x05 = 4db/s 0x03 = 2db/s 1514131211109876543210 rsvd rate bits field rw reset definition 15:12 rsvd ro 0x0 reserved 11:0 rate rw 0x50 avc decay rate this is the rate at which t he avc releases the attenuation previously applied to the signal during attack. avc decay rate is programmable. to use a custom rate, use the formula below to convert from db/s to hex value: hex value = (1 - (10^(-(rate_dbs/( 20*sys_fs)))) * 2^23 where, sys_fs is the system sa mple rate co nfigured in chip_clk_ctrl register. example values: 0x284 = 32db/s 0xa0 = 8db/s 0x50 = 4db/s 0x28 = 2db/s 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20 -bit filter coefficient that needs to be written bits field rw reset definition
sgtl5000 ea2 ds-0-3 83 sgtl5000 datasheet 7.0.0.45. dap_coef_wr_b1_lsb 0x012e 7.0.0.46. dap_coef_wr_b2_msb 0x0130 7.0.0.47. dap_coef_wr_b2_lsb 0x0132 7.0.0.48. dap_coef_wr_a1_msb 0x0134 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20 -bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20 -bit filter coefficient that needs to be written 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20 -bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20 -bit filter coefficient that needs to be written
84 sgtl5000 ea2 ds-0-3 sgtl5000 datasheet 7.0.0.49. dap_coef_wr_a1_lsb 0x0136 7.0.0.50. dap_coef_wr_a2_msb 0x0138 7.0.0.51. dap_coef_wr_a2_lsb 0x013a 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20 -bit filter coefficient that needs to be written. 1514131211109876543210 msb bits field rw reset definition 15:0 msb rw 0x0 most significant 16-bits of the 20 -bit filter coefficient that needs to be written 1514131211109876543210 rsvd lsb bits field rw reset definition 15:4 rsvd ro 0x0 reserved 3:0 lsb rw 0x0 least significant 4 bits of the 20 -bit filter coefficient that needs to be written.

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